drm/amd/pm: move those code piece used by Stoney only to smu8_hwmgr.c

Instead of putting them in amdgpu_dpm.c.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
index fd2a7a2..88909b7 100644 (file)
--- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
@@ -32,8 +32,6 @@
 #include "hwmgr.h"
 #include <linux/power_supply.h>
 
-#define WIDTH_4K 3840
-
 #define amdgpu_dpm_enable_bapm(adev, e) \
                ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e)))
 
@@ -386,18 +384,6 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
        if (ret)
                DRM_ERROR("Dpm %s uvd failed, ret = %d. \n",
                          enable ? "enable" : "disable", ret);
-
-       /* enable/disable Low Memory PState for UVD (4k videos) */
-       if (adev->asic_type == CHIP_STONEY &&
-               adev->uvd.decode_image_width >= WIDTH_4K) {
-               struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
-
-               if (hwmgr && hwmgr->hwmgr_func &&
-                   hwmgr->hwmgr_func->update_nbdpm_pstate)
-                       hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr,
-                                                              !enable,
-                                                              true);
-       }
 }
 
 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)

diff --git a/drivers/gpu/drm/amd/pm/inc/hwmgr.h b/drivers/gpu/drm/amd/pm/inc/hwmgr.h
index 8ed0107..03226ba 100644 (file)
--- a/drivers/gpu/drm/amd/pm/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/pm/inc/hwmgr.h
@@ -331,9 +331,6 @@ struct pp_hwmgr_func {
                                        uint32_t mc_addr_low,
                                        uint32_t mc_addr_hi,
                                        uint32_t size);
-       int (*update_nbdpm_pstate)(struct pp_hwmgr *hwmgr,
-                                       bool enable,
-                                       bool lock);
        int (*get_thermal_temperature_range)(struct pp_hwmgr *hwmgr,
                                        struct PP_TemperatureRange *range);
        int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf);

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
index 03bf8f0..b50fd4a 100644 (file)
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
@@ -1950,9 +1950,12 @@ static void smu8_dpm_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate)
                smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ACPPowerON, NULL);
 }
 
+#define WIDTH_4K               3840
+
 static void smu8_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
 {
        struct smu8_hwmgr *data = hwmgr->backend;
+       struct amdgpu_device *adev = hwmgr->adev;
 
        data->uvd_power_gated = bgate;
 
@@ -1976,6 +1979,12 @@ static void smu8_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
                smu8_dpm_update_uvd_dpm(hwmgr, false);
        }
 
+       /* enable/disable Low Memory PState for UVD (4k videos) */
+       if (adev->asic_type == CHIP_STONEY &&
+           adev->uvd.decode_image_width >= WIDTH_4K)
+               smu8_nbdpm_pstate_enable_disable(hwmgr,
+                                                bgate,
+                                                true);
 }
 
 static void smu8_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
@@ -2037,7 +2046,6 @@ static const struct pp_hwmgr_func smu8_hwmgr_funcs = {
        .power_state_set = smu8_set_power_state_tasks,
        .dynamic_state_management_disable = smu8_disable_dpm_tasks,
        .notify_cac_buffer_info = smu8_notify_cac_buffer_info,
-       .update_nbdpm_pstate = smu8_nbdpm_pstate_enable_disable,
        .get_thermal_temperature_range = smu8_get_thermal_temperature_range,
 };