IB/hfi1: Move saving PCI values to a separate function

During PCIe initialization some registers' values from
PCI config space are saved in order to restore them later
(i.e. after reset). Restoring those value is done by a
function called restore_pci_variables, while saving them
is put directly into function hfi1_pcie_ddinit.
Move saving values to a separate function in the image
of restoring functionality.

Reviewed-by: Jakub Byczkowski <jakub.byczkowski@intel.com>
Reviewed-by: Mike Marciniszyn <mike.marciniszyn@intel.com>
Signed-off-by: Bartlomiej Dudek <bartlomiej.dudek@intel.com>
Signed-off-by: Dennis Dalessandro <dennis.dalessandro@intel.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>

diff --git a/drivers/infiniband/hw/hfi1/chip.c b/drivers/infiniband/hw/hfi1/chip.c
index 789dbc4..4a4405e 100644 (file)
--- a/drivers/infiniband/hw/hfi1/chip.c
+++ b/drivers/infiniband/hw/hfi1/chip.c
@@ -14866,6 +14866,11 @@ struct hfi1_devdata *hfi1_init_dd(struct pci_dev *pdev,
        if (ret < 0)
                goto bail_free;
 
+       /* Save PCI space registers to rewrite after device reset */
+       ret = save_pci_variables(dd);
+       if (ret < 0)
+               goto bail_cleanup;
+
        /* verify that reads actually work, save revision for reset check */
        dd->revision = read_csr(dd, CCE_REVISION);
        if (dd->revision == ~(u64)0) {

diff --git a/drivers/infiniband/hw/hfi1/hfi.h b/drivers/infiniband/hw/hfi1/hfi.h
index 2ce3fc5..2d32c5c 100644 (file)
--- a/drivers/infiniband/hw/hfi1/hfi.h
+++ b/drivers/infiniband/hw/hfi1/hfi.h
@@ -1835,6 +1835,7 @@ void hfi1_pcie_ddcleanup(struct hfi1_devdata *);
 int pcie_speeds(struct hfi1_devdata *dd);
 int request_msix(struct hfi1_devdata *dd, u32 msireq);
 int restore_pci_variables(struct hfi1_devdata *dd);
+int save_pci_variables(struct hfi1_devdata *dd);
 int do_pcie_gen3_transition(struct hfi1_devdata *dd);
 int parse_platform_config(struct hfi1_devdata *dd);
 int get_platform_config_field(struct hfi1_devdata *dd,

diff --git a/drivers/infiniband/hw/hfi1/pcie.c b/drivers/infiniband/hw/hfi1/pcie.c
index cc7be22..82447b7 100644 (file)
--- a/drivers/infiniband/hw/hfi1/pcie.c
+++ b/drivers/infiniband/hw/hfi1/pcie.c
@@ -221,63 +221,11 @@ int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev)
        }
        dd_dev_info(dd, "WC RcvArray: %p for %x\n",
                    dd->rcvarray_wc, dd->chip_rcv_array_count * 8);
-       /*
-        * Save BARs and command to rewrite after device reset.
-        */
-
-       ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, &dd->pcibar0);
-       if (ret)
-               goto read_error;
-
-       ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, &dd->pcibar1);
-       if (ret)
-               goto read_error;
-
-       ret = pci_read_config_dword(dd->pcidev, PCI_ROM_ADDRESS, &dd->pci_rom);
-       if (ret)
-               goto read_error;
-
-       ret = pci_read_config_word(dd->pcidev, PCI_COMMAND, &dd->pci_command);
-       if (ret)
-               goto read_error;
-
-       ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL,
-                                       &dd->pcie_devctl);
-       if (ret)
-               goto read_error;
-
-       ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL,
-                                       &dd->pcie_lnkctl);
-       if (ret)
-               goto read_error;
-
-       ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL2,
-                                       &dd->pcie_devctl2);
-       if (ret)
-               goto read_error;
-
-       ret = pci_read_config_dword(dd->pcidev, PCI_CFG_MSIX0, &dd->pci_msix0);
-       if (ret)
-               goto read_error;
-
-       ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE1,
-                                   &dd->pci_lnkctl3);
-       if (ret)
-               goto read_error;
-
-       ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_TPH2, &dd->pci_tph2);
-       if (ret)
-               goto read_error;
 
        dd->flags |= HFI1_PRESENT;      /* chip.c CSR routines now work */
        return 0;
-
-read_error:
-       dd_dev_err(dd, "Unable to read from PCI config\n");
-       goto bail_error;
 nomem:
        ret = -ENOMEM;
-bail_error:
        hfi1_pcie_ddcleanup(dd);
        return ret;
 }
@@ -484,6 +432,64 @@ error:
        return ret;
 }
 
+/* Save BARs and command to rewrite after device reset */
+int save_pci_variables(struct hfi1_devdata *dd)
+{
+       int ret = 0;
+
+       ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
+                                   &dd->pcibar0);
+       if (ret)
+               goto error;
+
+       ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
+                                   &dd->pcibar1);
+       if (ret)
+               goto error;
+
+       ret = pci_read_config_dword(dd->pcidev, PCI_ROM_ADDRESS, &dd->pci_rom);
+       if (ret)
+               goto error;
+
+       ret = pci_read_config_word(dd->pcidev, PCI_COMMAND, &dd->pci_command);
+       if (ret)
+               goto error;
+
+       ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL,
+                                       &dd->pcie_devctl);
+       if (ret)
+               goto error;
+
+       ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL,
+                                       &dd->pcie_lnkctl);
+       if (ret)
+               goto error;
+
+       ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL2,
+                                       &dd->pcie_devctl2);
+       if (ret)
+               goto error;
+
+       ret = pci_read_config_dword(dd->pcidev, PCI_CFG_MSIX0, &dd->pci_msix0);
+       if (ret)
+               goto error;
+
+       ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE1,
+                                   &dd->pci_lnkctl3);
+       if (ret)
+               goto error;
+
+       ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_TPH2, &dd->pci_tph2);
+       if (ret)
+               goto error;
+
+       return 0;
+
+error:
+       dd_dev_err(dd, "Unable to read from PCI config\n");
+       return ret;
+}
+
 /*
  * BIOS may not set PCIe bus-utilization parameters for best performance.
  * Check and optionally adjust them to maximize our throughput.