arm: dts: imx8mn, imx8mn-beacon: Sync dts files with Kernel 5.12-rc5

There have been a few updates including flexspi, so it's necessary
to re-sync.

Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/arch/arm/dts/imx8mn-beacon-baseboard.dtsi b/arch/arm/dts/imx8mn-beacon-baseboard.dtsi
index 49bff19..376ca8f 100644 (file)
--- a/arch/arm/dts/imx8mn-beacon-baseboard.dtsi
+++ b/arch/arm/dts/imx8mn-beacon-baseboard.dtsi
@@ -34,6 +34,15 @@
                };
        };
 
+       reg_audio: regulator-audio {
+               compatible = "regulator-fixed";
+               regulator-name = "3v3_aud";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
        reg_usdhc2_vmmc: regulator-usdhc2 {
                compatible = "regulator-fixed";
                regulator-name = "vsd_3v3";
@@ -53,6 +62,20 @@
                gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
                enable-active-high;
        };
+
+       sound {
+               compatible = "fsl,imx-audio-wm8962";
+               model = "wm8962-audio";
+               audio-cpu = <&sai3>;
+               audio-codec = <&wm8962>;
+               audio-routing =
+                       "Headphone Jack", "HPOUTL",
+                       "Headphone Jack", "HPOUTR",
+                       "Ext Spk", "SPKOUTL",
+                       "Ext Spk", "SPKOUTR",
+                       "AMIC", "MICBIAS",
+                       "IN3R", "AMIC";
+       };
 };
 
 &ecspi2 {
@@ -98,6 +121,44 @@
                interrupt-parent = <&gpio4>;
                interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
        };
+
+       wm8962: audio-codec@1a {
+               compatible = "wlf,wm8962";
+               reg = <0x1a>;
+               clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
+               clock-names = "xclk";
+               DCVDD-supply = <&reg_audio>;
+               DBVDD-supply = <&reg_audio>;
+               AVDD-supply = <&reg_audio>;
+               CPVDD-supply = <&reg_audio>;
+               MICVDD-supply = <&reg_audio>;
+               PLLVDD-supply = <&reg_audio>;
+               SPKVDD1-supply = <&reg_audio>;
+               SPKVDD2-supply = <&reg_audio>;
+               gpio-cfg = <
+                       0x0000 /* 0:Default */
+                       0x0000 /* 1:Default */
+                       0x0000 /* 2:FN_DMICCLK */
+                       0x0000 /* 3:Default */
+                       0x0000 /* 4:FN_DMICCDAT */
+                       0x0000 /* 5:Default */
+               >;
+       };
+};
+
+&easrc {
+       fsl,asrc-rate  = <48000>;
+       status = "okay";
+};
+
+&sai3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_sai3>;
+       assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
+       assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
+       assigned-clock-rates = <24576000>;
+       fsl,sai-mclk-direction-output;
+       status = "okay";
 };
 
 &snvs_pwrkey {
@@ -177,6 +238,16 @@
                >;
        };
 
+       pinctrl_sai3: sai3grp {
+               fsl,pins = <
+                       MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
+                       MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
+                       MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
+                       MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
+                       MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0     0xd6
+               >;
+       };
+
        pinctrl_uart2: uart2grp {
                fsl,pins = <
                        MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140

diff --git a/arch/arm/dts/imx8mn-beacon-som.dtsi b/arch/arm/dts/imx8mn-beacon-som.dtsi
index 52a50d9..de2cd0e 100644 (file)
--- a/arch/arm/dts/imx8mn-beacon-som.dtsi
+++ b/arch/arm/dts/imx8mn-beacon-som.dtsi
@@ -4,6 +4,12 @@
  */
 
 / {
+       aliases {
+               rtc0 = &rtc;
+               rtc1 = &snvs_rtc;
+               spi0 = &flexspi;
+       };
+
        usdhc1_pwrseq: usdhc1_pwrseq {
                compatible = "mmc-pwrseq-simple";
                pinctrl-names = "default";
@@ -36,11 +42,39 @@
        cpu-supply = <&buck2_reg>;
 };
 
+/* DDR controller is running LPDDR at 800MHz which requires 0.95V */
+&a53_opp_table {
+       opp-1200000000 {
+               opp-microvolt = <950000>;
+       };
+};
+
+&ddrc {
+       operating-points-v2 = <&ddrc_opp_table>;
+
+       ddrc_opp_table: opp-table {
+               compatible = "operating-points-v2";
+
+               opp-25M {
+                       opp-hz = /bits/ 64 <25000000>;
+               };
+
+               opp-100M {
+                       opp-hz = /bits/ 64 <100000000>;
+               };
+
+               opp-800M {
+                       opp-hz = /bits/ 64 <800000000>;
+               };
+       };
+};
+
 &fec1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_fec1>;
        phy-mode = "rgmii-id";
        phy-handle = <&ethphy0>;
+       phy-supply = <&buck6_reg>;
        phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
        fsl,magic-packet;
        status = "okay";
@@ -56,6 +90,22 @@
        };
 };
 
+&flexspi {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexspi>;
+       status = "okay";
+
+       flash@0 {
+               reg = <0>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "jedec,spi-nor";
+               spi-max-frequency = <80000000>;
+               spi-tx-bus-width = <4>;
+               spi-rx-bus-width = <4>;
+       };
+};
+
 &i2c1 {
        clock-frequency = <400000>;
        pinctrl-names = "default";
@@ -184,7 +234,7 @@
                reg = <0x50>;
        };
 
-       rtc@51 {
+       rtc: rtc@51 {
                compatible = "nxp,pcf85263";
                reg = <0x51>;
        };
@@ -285,6 +335,17 @@
                >;
        };
 
+       pinctrl_flexspi: flexspigrp {
+               fsl,pins = <
+                       MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2
+                       MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82
+                       MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82
+                       MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82
+                       MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82
+                       MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82
+               >;
+       };
+
        pinctrl_pmic: pmicirqgrp {
                fsl,pins = <
                        MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3               0x141

diff --git a/arch/arm/dts/imx8mn.dtsi b/arch/arm/dts/imx8mn.dtsi
index ee17902..16ea500 100644 (file)
--- a/arch/arm/dts/imx8mn.dtsi
+++ b/arch/arm/dts/imx8mn.dtsi
@@ -241,10 +241,12 @@
        };
 
        soc@0 {
-               compatible = "simple-bus";
+               compatible = "fsl,imx8mn-soc", "simple-bus";
                #address-cells = <1>;
                #size-cells = <1>;
                ranges = <0x0 0x0 0x0 0x3e000000>;
+               nvmem-cells = <&imx8mn_uid>;
+               nvmem-cell-names = "soc_unique_id";
 
                aips1: bus@30000000 {
                        compatible = "fsl,aips-bus", "simple-bus";
@@ -253,7 +255,7 @@
                        #size-cells = <1>;
                        ranges;
 
-                       spba: bus@30000000 {
+                       spba: spba-bus@30000000 {
                                compatible = "fsl,spba-bus", "simple-bus";
                                #address-cells = <1>;
                                #size-cells = <1>;
@@ -531,9 +533,17 @@
                                #address-cells = <1>;
                                #size-cells = <1>;
 
+                               imx8mn_uid: unique-id@410 {
+                                       reg = <0x4 0x8>;
+                               };
+
                                cpu_speed_grade: speed-grade@10 {
                                        reg = <0x10 4>;
                                };
+
+                               fec_mac_address: mac-address@90 {
+                                       reg = <0x90 6>;
+                               };
                        };
 
                        anatop: anatop@30360000 {
@@ -581,7 +591,9 @@
                                                <&clk IMX8MN_CLK_NOC>,
                                                <&clk IMX8MN_CLK_AUDIO_AHB>,
                                                <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
-                                               <&clk IMX8MN_SYS_PLL3>;
+                                               <&clk IMX8MN_SYS_PLL3>,
+                                               <&clk IMX8MN_AUDIO_PLL1>,
+                                               <&clk IMX8MN_AUDIO_PLL2>;
                                assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
                                                         <&clk IMX8MN_ARM_PLL_OUT>,
                                                         <&clk IMX8MN_SYS_PLL3_OUT>,
@@ -589,7 +601,9 @@
                                assigned-clock-rates = <0>, <0>, <0>,
                                                        <400000000>,
                                                        <400000000>,
-                                                       <600000000>;
+                                                       <600000000>,
+                                                       <393216000>,
+                                                       <361267200>;
                        };
 
                        src: reset-controller@30390000 {
@@ -875,6 +889,19 @@
                                status = "disabled";
                        };
 
+                       flexspi: spi@30bb0000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "nxp,imx8mm-fspi";
+                               reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
+                               reg-names = "fspi_base", "fspi_mmap";
+                               interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MN_CLK_QSPI_ROOT>,
+                                        <&clk IMX8MN_CLK_QSPI_ROOT>;
+                               clock-names = "fspi", "fspi_en";
+                               status = "disabled";
+                       };
+
                        sdma1: dma-controller@30bd0000 {
                                compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
                                reg = <0x30bd0000 0x10000>;
@@ -903,13 +930,18 @@
                                assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
                                                  <&clk IMX8MN_CLK_ENET_TIMER>,
                                                  <&clk IMX8MN_CLK_ENET_REF>,
-                                                 <&clk IMX8MN_CLK_ENET_TIMER>;
+                                                 <&clk IMX8MN_CLK_ENET_PHY_REF>;
                                assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
                                                         <&clk IMX8MN_SYS_PLL2_100M>,
-                                                        <&clk IMX8MN_SYS_PLL2_125M>;
-                               assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
+                                                        <&clk IMX8MN_SYS_PLL2_125M>,
+                                                        <&clk IMX8MN_SYS_PLL2_50M>;
+                               assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
                                fsl,num-tx-queues = <3>;
                                fsl,num-rx-queues = <3>;
+                               nvmem-cells = <&fec_mac_address>;
+                               nvmem-cell-names = "mac-address";
+                               nvmem_macaddr_swap;
+                               fsl,stop-mode = <&gpr 0x10 3>;
                                status = "disabled";
                        };