clk: nuvoton: Add clk-ma35d1.h for driver extern functions
authorJacky Huang <ychuang3@nuvoton.com>
Thu, 22 Jun 2023 14:13:41 +0000 (14:13 +0000)
committerArnd Bergmann <arnd@arndb.de>
Thu, 22 Jun 2023 15:02:50 +0000 (17:02 +0200)
Moved the declaration of extern functions ma35d1_reg_clk_pll() and
ma35d1_reg_adc_clkdiv() from the .c files to the newly created header
file clk-ma35d1.h.

Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
drivers/clk/nuvoton/clk-ma35d1-divider.c
drivers/clk/nuvoton/clk-ma35d1-pll.c
drivers/clk/nuvoton/clk-ma35d1.c
drivers/clk/nuvoton/clk-ma35d1.h [new file with mode: 0644]

index 0c2bed4..bb8c23d 100644 (file)
@@ -9,6 +9,8 @@
 #include <linux/regmap.h>
 #include <linux/spinlock.h>
 
+#include "clk-ma35d1.h"
+
 struct ma35d1_adc_clk_div {
        struct clk_hw hw;
        void __iomem *reg;
@@ -20,11 +22,6 @@ struct ma35d1_adc_clk_div {
        spinlock_t *lock;
 };
 
-struct clk_hw *ma35d1_reg_adc_clkdiv(struct device *dev, const char *name,
-                                    struct clk_hw *parent_hw, spinlock_t *lock,
-                                    unsigned long flags, void __iomem *reg,
-                                    u8 shift, u8 width, u32 mask_bit);
-
 static inline struct ma35d1_adc_clk_div *to_ma35d1_adc_clk_div(struct clk_hw *_hw)
 {
        return container_of(_hw, struct ma35d1_adc_clk_div, hw);
index e4c9f94..ff3fb8b 100644 (file)
@@ -15,6 +15,8 @@
 #include <linux/units.h>
 #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
 
+#include "clk-ma35d1.h"
+
 /* PLL frequency limits */
 #define PLL_FREF_MAX_FREQ      (200 * HZ_PER_MHZ)
 #define PLL_FREF_MIN_FREQ      (1 * HZ_PER_MHZ)
@@ -71,9 +73,6 @@ struct ma35d1_clk_pll {
        void __iomem *ctl2_base;
 };
 
-struct clk_hw *ma35d1_reg_clk_pll(struct device *dev, u32 id, u8 u8mode, const char *name,
-                                 struct clk_hw *parent_hw, void __iomem *base);
-
 static inline struct ma35d1_clk_pll *to_ma35d1_clk_pll(struct clk_hw *_hw)
 {
        return container_of(_hw, struct ma35d1_clk_pll, hw);
index 297b115..8dfa762 100644 (file)
@@ -12,6 +12,8 @@
 #include <linux/spinlock.h>
 #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
 
+#include "clk-ma35d1.h"
+
 static DEFINE_SPINLOCK(ma35d1_lock);
 
 #define PLL_MAX_NUM            5
@@ -60,14 +62,6 @@ static DEFINE_SPINLOCK(ma35d1_lock);
 #define PLL_MODE_FRAC           1
 #define PLL_MODE_SS             2
 
-struct clk_hw *ma35d1_reg_clk_pll(struct device *dev, u32 id, u8 u8mode,
-                                 const char *name, struct clk_hw *parent_hw,
-                                 void __iomem *base);
-struct clk_hw *ma35d1_reg_adc_clkdiv(struct device *dev, const char *name,
-                                    struct clk_hw *hw, spinlock_t *lock,
-                                    unsigned long flags, void __iomem *reg,
-                                    u8 shift, u8 width, u32 mask_bit);
-
 static const struct clk_parent_data ca35clk_sel_clks[] = {
        { .index = 0 },  /* HXT */
        { .index = 1 },  /* CAPLL */
diff --git a/drivers/clk/nuvoton/clk-ma35d1.h b/drivers/clk/nuvoton/clk-ma35d1.h
new file mode 100644 (file)
index 0000000..3adee44
--- /dev/null
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2023 Nuvoton Technology Corp.
+ * Author: Chi-Fang Li <cfli0@nuvoton.com>
+ */
+
+#ifndef __DRV_CLK_NUVOTON_MA35D1_H
+#define __DRV_CLK_NUVOTON_MA35D1_H
+
+struct clk_hw *ma35d1_reg_clk_pll(struct device *dev, u32 id, u8 u8mode, const char *name,
+                                 struct clk_hw *parent_hw, void __iomem *base);
+
+struct clk_hw *ma35d1_reg_adc_clkdiv(struct device *dev, const char *name,
+                                    struct clk_hw *parent_hw, spinlock_t *lock,
+                                    unsigned long flags, void __iomem *reg,
+                                    u8 shift, u8 width, u32 mask_bit);
+
+#endif /* __DRV_CLK_NUVOTON_MA35D1_H */