net: ethernet: mediatek: move mt7623 settings out off the mt7530

Moving mt7623 logic out off mt7530, is required to make hardware setting
consistent after we introduce phylink to mtk driver.

Fixes: b8fc9f30821e ("net: ethernet: mediatek: Add basic PHYLINK support")
Reviewed-by: Sean Wang <sean.wang@mediatek.com>
Tested-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: René van Dorst <opensource@vdorst.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 8d28f90..0904710 100644 (file)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -65,6 +65,17 @@ u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
        return __raw_readl(eth->base + reg);
 }
 
+u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg)
+{
+       u32 val;
+
+       val = mtk_r32(eth, reg);
+       val &= ~mask;
+       val |= set;
+       mtk_w32(eth, val, reg);
+       return reg;
+}
+
 static int mtk_mdio_busy_wait(struct mtk_eth *eth)
 {
        unsigned long t_start = jiffies;
@@ -193,7 +204,7 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
        struct mtk_mac *mac = container_of(config, struct mtk_mac,
                                           phylink_config);
        struct mtk_eth *eth = mac->hw;
-       u32 mcr_cur, mcr_new, sid;
+       u32 mcr_cur, mcr_new, sid, i;
        int val, ge_mode, err;
 
        /* MT76x8 has no hardware settings between for the MAC */
@@ -255,6 +266,17 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
                                    PHY_INTERFACE_MODE_TRGMII)
                                        mtk_gmac0_rgmii_adjust(mac->hw,
                                                               state->speed);
+
+                               /* mt7623_pad_clk_setup */
+                               for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
+                                       mtk_w32(mac->hw,
+                                               TD_DM_DRVP(8) | TD_DM_DRVN(8),
+                                               TRGMII_TD_ODT(i));
+
+                               /* Assert/release MT7623 RXC reset */
+                               mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL,
+                                       TRGMII_RCK_CTRL);
+                               mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL);
                        }
                }
 

diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 85830fe..454cfcd 100644 (file)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -352,10 +352,13 @@
 #define DQSI0(x)               ((x << 0) & GENMASK(6, 0))
 #define DQSI1(x)               ((x << 8) & GENMASK(14, 8))
 #define RXCTL_DMWTLAT(x)       ((x << 16) & GENMASK(18, 16))
+#define RXC_RST                        BIT(31)
 #define RXC_DQSISEL            BIT(30)
 #define RCK_CTRL_RGMII_1000    (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16))
 #define RCK_CTRL_RGMII_10_100  RXCTL_DMWTLAT(2)
 
+#define NUM_TRGMII_CTRL                5
+
 /* TRGMII RXC control register */
 #define TRGMII_TCK_CTRL                0x10340
 #define TXCTL_DMWTLAT(x)       ((x << 16) & GENMASK(18, 16))
@@ -363,6 +366,11 @@
 #define TCK_CTRL_RGMII_1000    TXCTL_DMWTLAT(2)
 #define TCK_CTRL_RGMII_10_100  (TXC_INV | TXCTL_DMWTLAT(2))
 
+/* TRGMII TX Drive Strength */
+#define TRGMII_TD_ODT(i)       (0x10354 + 8 * (i))
+#define  TD_DM_DRVP(x)         ((x) & 0xf)
+#define  TD_DM_DRVN(x)         (((x) & 0xf) << 4)
+
 /* TRGMII Interface mode register */
 #define INTF_MODE              0x10390
 #define TRGMII_INTF_DIS                BIT(0)