video: vpp: add vd afbc YUV 422/444 support for tl1 [1/1]

PD#172587

Problem:
Bringup TL1 vidoe driver.
TL1 need support YUV422/444 AFBC.
TL1 need check afbc source from decode or vdin.
TL1 need afbc compress loss mode.

Solution:
Merge from branch bringup/amlogic-4.9/tl1-20181111.

Verify:
verify on tl1

Change-Id: I0af62e7638db4e1c349df874ccffdeddcaa715af
Signed-off-by: Brian Zhu <brian.zhu@amlogic.com>

diff --git a/drivers/amlogic/media/video_sink/video.c b/drivers/amlogic/media/video_sink/video.c
index 6dceea4..0c1b205 100644 (file)
--- a/drivers/amlogic/media/video_sink/video.c
+++ b/drivers/amlogic/media/video_sink/video.c
@@ -1810,7 +1810,7 @@ static void zoom_get_vert_pos(struct vframe_s *vf, u32 vpp_3d_mode, u32 *ls,
 }
 
 #endif
-static void zoom_display_horz(int hscale)
+static void zoom_display_horz(struct vframe_s *vf, int hscale)
 {
        u32 ls = 0, le = 0, rs = 0, re = 0;
 #ifdef TV_REVERSE
@@ -1818,7 +1818,7 @@ static void zoom_display_horz(int hscale)
 #endif
 #ifdef TV_3D_FUNCTION_OPEN
        if (process_3d_type & MODE_3D_ENABLE) {
-               zoom_get_horz_pos(cur_dispbuf, cur_frame_par->vpp_3d_mode, &ls,
+               zoom_get_horz_pos(vf, cur_frame_par->vpp_3d_mode, &ls,
                                  &le, &rs, &re);
        } else {
                ls = rs = zoom_start_x_lines;
@@ -1854,6 +1854,13 @@ static void zoom_display_horz(int hscale)
                int l_aligned;
                int r_aligned;
                int h_skip = cur_frame_par->hscale_skip_count + 1;
+               int c_skip = 2;
+
+               /* After TL1, afbc supports 420/422/444*/
+               if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1))
+                       if (vf && (vf->type & VIDTYPE_VIU_444))
+                               c_skip = 1;
+
                if ((zoom_start_x_lines > 0) ||
                (zoom_end_x_lines < ori_end_x_lines)) {
                        l_aligned = round_down(ori_start_x_lines, 32);
@@ -1864,7 +1871,7 @@ static void zoom_display_horz(int hscale)
                }
                VSYNC_WR_MPEG_REG(AFBC_VD_CFMT_W,
                          (((r_aligned - l_aligned) / h_skip) << 16) |
-                         ((r_aligned / 2 - l_aligned / 2) / h_skip));
+                         ((r_aligned / c_skip - l_aligned / c_skip) / h_skip));
 
                VSYNC_WR_MPEG_REG(AFBC_MIF_HOR_SCOPE,
                          ((l_aligned / 32) << 16) |
@@ -1924,7 +1931,7 @@ static void zoom_display_horz(int hscale)
                1) >> hscale) << VD1_FMT_CHROMA_WIDTH_BIT));
 }
 
-static void vd2_zoom_display_horz(int hscale)
+static void vd2_zoom_display_horz(struct vframe_s *vf, int hscale)
 {
        u32 ls, le, rs, re;
 #ifdef TV_REVERSE
@@ -1937,6 +1944,12 @@ static void vd2_zoom_display_horz(int hscale)
                int l_aligned;
                int r_aligned;
                int h_skip = cur_frame_par->hscale_skip_count + 1;
+               int c_skip = 2;
+
+               /* After TL1, afbc supports 420/422/444*/
+               if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1))
+                       if (vf && (vf->type & VIDTYPE_VIU_444))
+                               c_skip = 1;
 
                if ((zoom2_start_x_lines > 0) ||
                (zoom2_end_x_lines < ori2_end_x_lines)) {
@@ -1948,7 +1961,7 @@ static void vd2_zoom_display_horz(int hscale)
                }
                VSYNC_WR_MPEG_REG(VD2_AFBC_VD_CFMT_W,
                          (((r_aligned - l_aligned) / h_skip) << 16) |
-                         ((r_aligned / 2 - l_aligned / 2) / h_skip));
+                         ((r_aligned / c_skip - l_aligned / c_skip) / h_skip));
 
                VSYNC_WR_MPEG_REG(VD2_AFBC_MIF_HOR_SCOPE,
                          ((l_aligned / 32) << 16) |
@@ -2007,14 +2020,14 @@ static void vd2_zoom_display_horz(int hscale)
                << VD1_FMT_CHROMA_WIDTH_BIT));
 }
 
-static void zoom_display_vert(void)
+static void zoom_display_vert(struct vframe_s *vf)
 {
 
        u32 ls, le, rs, re;
 
        /*if (platform_type == 1) {*/
                if (process_3d_type & MODE_3D_ENABLE) {
-                       zoom_get_vert_pos(cur_dispbuf,
+                       zoom_get_vert_pos(vf,
                        cur_frame_par->vpp_3d_mode, &ls,
                                          &le, &rs, &re);
                } else {
@@ -2033,7 +2046,7 @@ static void zoom_display_vert(void)
        }
 */
 
-       if ((cur_dispbuf) && (cur_dispbuf->type & VIDTYPE_MVC)) {
+       if ((vf) && (vf->type & VIDTYPE_MVC)) {
                if (is_need_framepacking_output()) {
                        VSYNC_WR_MPEG_REG(
                                VD1_IF0_LUMA_Y0 + cur_dev->viu_off,
@@ -2125,13 +2138,21 @@ static void zoom_display_vert(void)
                int ori_t_aligned;
                int ori_b_aligned;
                int v_skip = cur_frame_par->vscale_skip_count + 1;
+               int c_skip = 2;
+
+               /* After TL1, afbc supports 420/422/444*/
+               if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1))
+                       if (vf && ((vf->type & VIDTYPE_VIU_444)
+                               || (vf->type & VIDTYPE_VIU_422)))
+                               c_skip = 1;
+
                t_aligned = round_down(zoom_start_y_lines, 4);
                b_aligned = round_up(zoom_end_y_lines + 1, 4);
 
                ori_t_aligned = round_down(ori_start_y_lines, 4);
                ori_b_aligned = round_up(ori_end_y_lines + 1, 4);
                VSYNC_WR_MPEG_REG(AFBC_VD_CFMT_H,
-                   (b_aligned - t_aligned) / 2 / v_skip);
+                   (b_aligned - t_aligned) / c_skip / v_skip);
 
                VSYNC_WR_MPEG_REG(AFBC_MIF_VER_SCOPE,
                    ((t_aligned / 4) << 16) |
@@ -2159,7 +2180,7 @@ static void zoom_display_vert(void)
        }
 }
 
-static void vd2_zoom_display_vert(void)
+static void vd2_zoom_display_vert(struct vframe_s *vf)
 {
 
        u32 ls, le, rs, re;
@@ -2194,6 +2215,14 @@ static void vd2_zoom_display_vert(void)
                int ori_t_aligned;
                int ori_b_aligned;
                int v_skip = cur_frame_par->vscale_skip_count + 1;
+               int c_skip = 2;
+
+               /* After TL1, afbc supports 420/422/444*/
+               if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1))
+                       if (vf && ((vf->type & VIDTYPE_VIU_444)
+                               || (vf->type & VIDTYPE_VIU_422)))
+                               c_skip = 1;
+
                t_aligned = round_down(zoom2_start_y_lines, 4);
                b_aligned = round_up(zoom2_end_y_lines + 1, 4);
 
@@ -2202,7 +2231,7 @@ static void vd2_zoom_display_vert(void)
 
                /* TODO: afbc setting only support 420 for now */
                VSYNC_WR_MPEG_REG(VD2_AFBC_VD_CFMT_H,
-                  (b_aligned - t_aligned) / 2 / v_skip);
+                  (b_aligned - t_aligned) / c_skip / v_skip);
 
                VSYNC_WR_MPEG_REG(VD2_AFBC_MIF_VER_SCOPE,
                    ((t_aligned / 4) << 16) |
@@ -3079,20 +3108,31 @@ static void viu_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
                                r |= 0xcc;
 #ifdef TV_REVERSE
                        if (reverse)
-                               r |= (1<<26)|(1<<27);
+                               r |= (1<<26) | (1<<27);
 #endif
                        if (vf->bitdepth & BITDEPTH_SAVING_MODE)
                                r |= (1<<28); /* mem_saving_mode */
                        if (type & VIDTYPE_SCATTER)
                                r |= (1<<29);
                        VSYNC_WR_MPEG_REG(AFBC_MODE, r);
-                       VSYNC_WR_MPEG_REG(AFBC_ENABLE, 0x1700);
+
+                       r = 0x1700;
+                       if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1)) {
+                               if (vf && (vf->source_type
+                                       != VFRAME_SOURCE_TYPE_HDMI))
+                                       r |= (1 << 19); /* dos_uncomp */
+                       }
+                       VSYNC_WR_MPEG_REG(AFBC_ENABLE, r);
 
                        r = 0x100;
-                       /* need check the vf->type 444/422/420 */
-                       /* current use 420 as default for tl1 */
-                       if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1))
-                               r |= (2 << 12);
+                       if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1)) {
+                               if (type & VIDTYPE_VIU_444)
+                                       r |= 0;
+                               else if (type & VIDTYPE_VIU_422)
+                                       r |= (1 << 12);
+                               else
+                                       r |= (2 << 12);
+                       }
                        VSYNC_WR_MPEG_REG(AFBC_CONV_CTRL, r);
 
                        u = (vf->bitdepth >> (BITDEPTH_U_SHIFT)) & 0x3;
@@ -3102,61 +3142,60 @@ static void viu_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
                                0x80 << (u + 10) |
                                0x80 << v);
                        /* chroma formatter */
-                       /* TODO: afbc setting only cover 420 for now */
-/*
-#ifdef TV_REVERSE
-                       if (reverse) {
+
+                       r = 0;
 #ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
-                               if (is_meson_txlx_package_962X()
+                       if (is_meson_txlx_package_962X()
                                && !is_dolby_vision_stb_mode()
-                               && is_dolby_vision_on())
-                                       VSYNC_WR_MPEG_REG(
-                                               AFBC_VD_CFMT_CTRL,
-                                               HFORMATTER_REPEAT |
-                                               HFORMATTER_YC_RATIO_2_1 |
-                                               HFORMATTER_EN |
-                                               VFORMATTER_ALWAYS_RPT |
-                                               (0 << VFORMATTER_INIPHASE_BIT) |
-                                               (0x8 << VFORMATTER_PHASE_BIT) |
-                                               VFORMATTER_EN);
-                               else
-#endif
-                                       VSYNC_WR_MPEG_REG(AFBC_VD_CFMT_CTRL,
-                                               HFORMATTER_REPEAT |
-                                       (0xc << VFORMATTER_INIPHASE_BIT) |
-                                               HFORMATTER_YC_RATIO_2_1 |
-                                               HFORMATTER_EN |
-                                               VFORMATTER_RPTLINE0_EN |
-                                               (0x8 << VFORMATTER_PHASE_BIT) |
-                                               VFORMATTER_EN);
+                               && is_dolby_vision_on()) {
+                               r = HFORMATTER_REPEAT |
+                                       HFORMATTER_YC_RATIO_2_1 |
+                                       HFORMATTER_EN |
+                                       VFORMATTER_ALWAYS_RPT |
+                                       (0 << VFORMATTER_INIPHASE_BIT) |
+                                       (0x8 << VFORMATTER_PHASE_BIT) |
+                                       VFORMATTER_EN;
                        } else
 #endif
-*/
-                       {
-#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
-                               if (is_meson_txlx_package_962X()
-                               && !is_dolby_vision_stb_mode()
-                               && is_dolby_vision_on())
+                       if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1)) {
+                               r = HFORMATTER_REPEAT |
+                                       HFORMATTER_YC_RATIO_2_1 |
+                                       HFORMATTER_EN |
+                                       VFORMATTER_RPTLINE0_EN |
+                                       (0xc << VFORMATTER_INIPHASE_BIT) |
+                                       (0x8 << VFORMATTER_PHASE_BIT) |
+                                       VFORMATTER_EN;
+                               if (type & VIDTYPE_VIU_444) {
+                                       r &= ~HFORMATTER_EN;
+                                       r &= ~VFORMATTER_EN;
+                                       r &= ~HFORMATTER_YC_RATIO_2_1;
+                               } else if (type & VIDTYPE_VIU_422) {
+                                       r &= ~VFORMATTER_EN;
+                               }
+                       } else {
+                               r = HFORMATTER_REPEAT |
+                                       HFORMATTER_YC_RATIO_2_1 |
+                                       HFORMATTER_EN |
+                                       VFORMATTER_RPTLINE0_EN |
+                                       (0xc << VFORMATTER_INIPHASE_BIT) |
+                                       (0x8 << VFORMATTER_PHASE_BIT) |
+                                       VFORMATTER_EN;
+                       }
+                       VSYNC_WR_MPEG_REG(AFBC_VD_CFMT_CTRL, r);
+
+                       if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1)) {
+                               if (type & VIDTYPE_COMPRESS_LOSS)
                                        VSYNC_WR_MPEG_REG(
-                                               AFBC_VD_CFMT_CTRL,
-                                               HFORMATTER_REPEAT |
-                                               HFORMATTER_YC_RATIO_2_1 |
-                                               HFORMATTER_EN |
-                                               VFORMATTER_ALWAYS_RPT |
-                                               (0 << VFORMATTER_INIPHASE_BIT) |
-                                               (0x8 << VFORMATTER_PHASE_BIT) |
-                                               VFORMATTER_EN);
+                                       AFBCDEC_IQUANT_ENABLE,
+                                       ((1 << 11) |
+                                       (1 << 10) |
+                                       (1 << 4) |
+                                       (1 << 0)));
                                else
-#endif
-                                       VSYNC_WR_MPEG_REG(AFBC_VD_CFMT_CTRL,
-                                               HFORMATTER_REPEAT |
-                                       (0xc << VFORMATTER_INIPHASE_BIT) |
-                                               HFORMATTER_YC_RATIO_2_1 |
-                                               HFORMATTER_EN |
-                                               VFORMATTER_RPTLINE0_EN |
-                                               (0x8 << VFORMATTER_PHASE_BIT) |
-                                               VFORMATTER_EN);
+                                       VSYNC_WR_MPEG_REG(
+                                       AFBCDEC_IQUANT_ENABLE, 0);
                        }
+
                        vd1_path_select(true);
 
                        VSYNC_WR_MPEG_REG(
@@ -3625,8 +3664,14 @@ static void vd2_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
        static const u32 vpat[MAX_VSKIP_COUNT + 1] = {
                0, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf};
        u32 u, v;
-       u32 type = vf->type, bit_mode = 0;
+       u32 type, bit_mode = 0;
+
+       if (!vf) {
+               pr_err("vd2_set_dcu vf is NULL\n");
+               return;
+       }
 
+       type = vf->type;
        pr_debug("set dcu for vd2 %p, type:0x%x\n", vf, type);
        last_el_w = (vf->type
                & VIDTYPE_COMPRESS) ?
@@ -3646,20 +3691,31 @@ static void vd2_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
 
 #ifdef TV_REVERSE
                        if (reverse)
-                               r |= (1<<26)|(1<<27);
+                               r |= (1<<26) | (1<<27);
 #endif
                        if (vf->bitdepth & BITDEPTH_SAVING_MODE)
                                r |= (1<<28); /* mem_saving_mode */
                        if (type & VIDTYPE_SCATTER)
                                r |= (1<<29);
                        VSYNC_WR_MPEG_REG(VD2_AFBC_MODE, r);
-                       VSYNC_WR_MPEG_REG(VD2_AFBC_ENABLE, 0x1700);
+
+                       r = 0x1700;
+                       if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1)) {
+                               if (vf && (vf->source_type
+                                       != VFRAME_SOURCE_TYPE_HDMI))
+                                       r |= (1 << 19); /* dos_uncomp */
+                       }
+                       VSYNC_WR_MPEG_REG(VD2_AFBC_ENABLE, r);
 
                        r = 0x100;
-                       /* need check the vf->type 444/422/420 */
-                       /* current use 420 as default for tl1 */
-                       if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1))
-                               r |= (2 << 12);
+                       if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1)) {
+                               if (type & VIDTYPE_VIU_444)
+                                       r |= 0;
+                               else if (type & VIDTYPE_VIU_422)
+                                       r |= (1 << 12);
+                               else
+                                       r |= (2 << 12);
+                       }
                        VSYNC_WR_MPEG_REG(VD2_AFBC_CONV_CTRL, r);
 
                        u = (vf->bitdepth >> (BITDEPTH_U_SHIFT)) & 0x3;
@@ -3668,67 +3724,73 @@ static void vd2_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
                                0x3FF00000 | /*Y,bit20+*/
                                0x80 << (u + 10) |
                                0x80 << v);
+
                        /* chroma formatter */
-                       /* TODO: afbc setting only cover 420 for now */
-#ifdef TV_REVERSE
-                       if (reverse) {
+                       r = HFORMATTER_EN |
+                               (0x8 << VFORMATTER_PHASE_BIT) |
+                               VFORMATTER_EN;
 #ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
-                               if (is_meson_txlx_package_962X()
+                       if (is_meson_txlx_package_962X()
                                && !is_dolby_vision_stb_mode()
                                && is_dolby_vision_on()) {
-                                       VSYNC_WR_MPEG_REG(
-                                               VD2_AFBC_VD_CFMT_CTRL,
-                                               HFORMATTER_REPEAT |
-                                               HFORMATTER_YC_RATIO_2_1 |
-                                               HFORMATTER_EN |
-                                               VFORMATTER_ALWAYS_RPT |
-                                               (0 << VFORMATTER_INIPHASE_BIT) |
-                                               (0x8 << VFORMATTER_PHASE_BIT) |
-                                               VFORMATTER_EN);
-                               } else
+                               r |= HFORMATTER_REPEAT |
+                                       HFORMATTER_YC_RATIO_2_1 |
+                                       HFORMATTER_EN |
+                                       VFORMATTER_ALWAYS_RPT |
+                                       (0 << VFORMATTER_INIPHASE_BIT) |
+                                       (0x8 << VFORMATTER_PHASE_BIT) |
+                                       VFORMATTER_EN;
+                       } else
 #endif
-                                       VSYNC_WR_MPEG_REG(VD2_AFBC_VD_CFMT_CTRL,
-                                       (is_dolby_vision_on() ?
-                                               HFORMATTER_REPEAT :
-                                               HFORMATTER_RRT_PIXEL0) |
-                                               HFORMATTER_YC_RATIO_2_1 |
-                                               HFORMATTER_EN |
-                                               VFORMATTER_RPTLINE0_EN |
-                                       (is_dolby_vision_on() ?
-                                       (0xc << VFORMATTER_INIPHASE_BIT) : 0) |
-                                               (0x8 << VFORMATTER_PHASE_BIT) |
-                                               VFORMATTER_EN);
+                       if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1)) {
+                               r = HFORMATTER_YC_RATIO_2_1 |
+                                       HFORMATTER_EN |
+                                       VFORMATTER_RPTLINE0_EN |
+                                       (0x8 << VFORMATTER_PHASE_BIT) |
+                                       VFORMATTER_EN;
+
+                               if (is_dolby_vision_on())
+                                       r |= HFORMATTER_REPEAT |
+                                       (0xc << VFORMATTER_INIPHASE_BIT);
+                               else
+                                       r |= HFORMATTER_RRT_PIXEL0 |
+                                       (0 << VFORMATTER_INIPHASE_BIT);
+
+                               if (type & VIDTYPE_VIU_444) {
+                                       r &= ~HFORMATTER_EN;
+                                       r &= ~VFORMATTER_EN;
+                                       r &= ~HFORMATTER_YC_RATIO_2_1;
+                               } else if (type & VIDTYPE_VIU_422) {
+                                       r &= ~VFORMATTER_EN;
+                               }
                        } else {
-#endif
-#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
-                               if (is_meson_txlx_package_962X()
-                               && !is_dolby_vision_stb_mode()
-                               && is_dolby_vision_on()) {
-                                       VSYNC_WR_MPEG_REG(
-                                               VD2_AFBC_VD_CFMT_CTRL,
-                                               HFORMATTER_REPEAT |
-                                               HFORMATTER_YC_RATIO_2_1 |
-                                               HFORMATTER_EN |
-                                               VFORMATTER_ALWAYS_RPT |
-                                               (0 << VFORMATTER_INIPHASE_BIT) |
-                                               (0x8 << VFORMATTER_PHASE_BIT) |
-                                               VFORMATTER_EN);
-                               } else
-#endif
-                                       VSYNC_WR_MPEG_REG(VD2_AFBC_VD_CFMT_CTRL,
-                                       (is_dolby_vision_on() ?
-                                       HFORMATTER_REPEAT :
-                                       HFORMATTER_RRT_PIXEL0) |
-                                       HFORMATTER_YC_RATIO_2_1 |
+                               r = HFORMATTER_YC_RATIO_2_1 |
                                        HFORMATTER_EN |
                                        VFORMATTER_RPTLINE0_EN |
-                                       (is_dolby_vision_on() ?
-                                       (0xc << VFORMATTER_INIPHASE_BIT) : 0) |
                                        (0x8 << VFORMATTER_PHASE_BIT) |
-                                       VFORMATTER_EN);
-#ifdef TV_REVERSE
+                                       VFORMATTER_EN;
+                               if (is_dolby_vision_on())
+                                       r |= HFORMATTER_REPEAT |
+                                       (0xc << VFORMATTER_INIPHASE_BIT);
+                               else
+                                       r |= HFORMATTER_RRT_PIXEL0 |
+                                       (0 << VFORMATTER_INIPHASE_BIT);
                        }
-#endif
+                       VSYNC_WR_MPEG_REG(VD2_AFBC_VD_CFMT_CTRL, r);
+
+                       if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1)) {
+                               if (type & VIDTYPE_COMPRESS_LOSS)
+                                       VSYNC_WR_MPEG_REG(
+                                       VD2_AFBCDEC_IQUANT_ENABLE,
+                                       ((1 << 11) |
+                                       (1 << 10) |
+                                       (1 << 4) |
+                                       (1 << 0)));
+                               else
+                                       VSYNC_WR_MPEG_REG(
+                                       VD2_AFBCDEC_IQUANT_ENABLE, 0);
+                       }
+
                        vd2_path_select(true);
                        VSYNC_WR_MPEG_REG(VD2_IF0_GEN_REG +
                                         cur_dev->viu_off, 0);
@@ -5957,11 +6019,12 @@ SET_FILTER:
                        zoom_start_x_lines =
                                        cur_frame_par->VPP_hd_start_lines_;
                        zoom_end_x_lines = cur_frame_par->VPP_hd_end_lines_;
-                       zoom_display_horz(cur_frame_par->hscale_skip_count);
+                       zoom_display_horz(cur_dispbuf,
+                               cur_frame_par->hscale_skip_count);
 
                        zoom_start_y_lines = zoom_start_y;
                        zoom_end_y_lines = zoom_end_y;
-                       zoom_display_vert();
+                       zoom_display_vert(cur_dispbuf);
                        if (is_dolby_vision_enable() && cur_dispbuf2) {
                                zoom2_start_x_lines = ori2_start_x_lines;
                                zoom2_end_x_lines = ori2_end_x_lines;
@@ -5969,8 +6032,8 @@ SET_FILTER:
                                zoom2_end_y_lines = ori2_end_y_lines;
                                correct_vd2_mif_size_for_DV(
                                        cur_frame_par, cur_dispbuf);
-                               vd2_zoom_display_horz(0);
-                               vd2_zoom_display_vert();
+                               vd2_zoom_display_horz(cur_dispbuf2, 0);
+                               vd2_zoom_display_vert(cur_dispbuf2);
                        }
                }
                /*vpp input size setting*/

diff --git a/include/linux/amlogic/media/registers/regs/viu_regs.h b/include/linux/amlogic/media/registers/regs/viu_regs.h
index 20d5df4..9f0299c 100644 (file)
--- a/include/linux/amlogic/media/registers/regs/viu_regs.h
+++ b/include/linux/amlogic/media/registers/regs/viu_regs.h
@@ -213,5 +213,18 @@
 #define G12_VD1_IF0_GEN_REG3 0x3216
 #define G12_VD2_IF0_GEN_REG3 0x3236
 
+/* TL1 */
+#define AFBCDEC_IQUANT_ENABLE 0x1af2
+#define AFBCDEC_IQUANT_LUT_1 0x1af3
+#define AFBCDEC_IQUANT_LUT_2 0x1af4
+#define AFBCDEC_IQUANT_LUT_3 0x1af5
+#define AFBCDEC_IQUANT_LUT_4 0x1af6
+
+#define VD2_AFBCDEC_IQUANT_ENABLE 0x3192
+#define VD2_AFBCDEC_IQUANT_LUT_1 0x3193
+#define VD2_AFBCDEC_IQUANT_LUT_2 0x3194
+#define VD2_AFBCDEC_IQUANT_LUT_3 0x3195
+#define VD2_AFBCDEC_IQUANT_LUT_4 0x3196
+
 #endif
 

diff --git a/include/linux/amlogic/media/vfm/vframe.h b/include/linux/amlogic/media/vfm/vframe.h
index c2936f3..2a62b67 100644 (file)
--- a/include/linux/amlogic/media/vfm/vframe.h
+++ b/include/linux/amlogic/media/vfm/vframe.h
@@ -45,6 +45,7 @@
 #define VIDTYPE_PIC                    0x200000
 #define VIDTYPE_SCATTER                 0x400000
 #define VIDTYPE_VD2                                            0x800000
+#define VIDTYPE_COMPRESS_LOSS          0x1000000
 
 #define DISP_RATIO_FORCECONFIG          0x80000000
 #define DISP_RATIO_FORCE_NORMALWIDE     0x40000000
@@ -280,18 +281,21 @@ struct vframe_pic_mode_s {
 #define BITDEPTH_Y8    (0 << BITDEPTH_Y_SHIFT)
 #define BITDEPTH_Y9    (1 << BITDEPTH_Y_SHIFT)
 #define BITDEPTH_Y10   (2 << BITDEPTH_Y_SHIFT)
+#define BITDEPTH_Y12   (3 << BITDEPTH_Y_SHIFT)
 #define BITDEPTH_YMASK (3 << BITDEPTH_Y_SHIFT)
 
 #define BITDEPTH_U_SHIFT 10
 #define BITDEPTH_U8    (0 << BITDEPTH_U_SHIFT)
 #define BITDEPTH_U9    (1 << BITDEPTH_U_SHIFT)
 #define BITDEPTH_U10   (2 << BITDEPTH_U_SHIFT)
+#define BITDEPTH_U12   (3 << BITDEPTH_U_SHIFT)
 #define BITDEPTH_UMASK (3 << BITDEPTH_U_SHIFT)
 
 #define BITDEPTH_V_SHIFT 12
 #define BITDEPTH_V8    (0 << BITDEPTH_V_SHIFT)
 #define BITDEPTH_V9    (1 << BITDEPTH_V_SHIFT)
 #define BITDEPTH_V10   (2 << BITDEPTH_V_SHIFT)
+#define BITDEPTH_V12   (3 << BITDEPTH_V_SHIFT)
 #define BITDEPTH_VMASK (3 << BITDEPTH_V_SHIFT)
 
 #define BITDEPTH_MASK (BITDEPTH_YMASK | BITDEPTH_UMASK | BITDEPTH_VMASK)