riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node
authorXingyu Wu <xingyu.wu@starfivetech.com>
Thu, 16 Mar 2023 03:05:14 +0000 (11:05 +0800)
committerJaehoon Chung <jh80.chung@samsung.com>
Mon, 24 Jul 2023 23:24:36 +0000 (08:24 +0900)
Add the PLL clock node for the Starfive JH7110 SoC and
modify the SYSCRG node to add PLL clocks.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
arch/riscv/boot/dts/starfive/jh7110.dtsi

index 196dc14..7e0de0a 100644 (file)
                                 <&gmac1_rgmii_rxin>,
                                 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
                                 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
-                                <&tdm_ext>, <&mclk_ext>;
+                                <&tdm_ext>, <&mclk_ext>,
+                                <&pllclk JH7110_CLK_PLL0_OUT>,
+                                <&pllclk JH7110_CLK_PLL1_OUT>,
+                                <&pllclk JH7110_CLK_PLL2_OUT>;
                        clock-names = "osc", "gmac1_rmii_refin",
                                      "gmac1_rgmii_rxin",
                                      "i2stx_bclk_ext", "i2stx_lrck_ext",
                                      "i2srx_bclk_ext", "i2srx_lrck_ext",
-                                     "tdm_ext", "mclk_ext";
+                                     "tdm_ext", "mclk_ext",
+                                     "pll0_out", "pll1_out", "pll2_out";
                        #clock-cells = <1>;
                        #reset-cells = <1>;
                };
 
                sys_syscon: syscon@13030000 {
-                       compatible = "starfive,jh7110-sys-syscon", "syscon";
+                       compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
                        reg = <0x0 0x13030000 0x0 0x1000>;
+
+                       pllclk: pll-clock-controller {
+                               compatible = "starfive,jh7110-pll";
+                               clocks = <&osc>;
+                               #clock-cells = <1>;
+                       };
                };
 
                sysgpio: pinctrl@13040000 {