freedreno/a6xx: Add a few registers

Based-on: https://patchwork.freedesktop.org/patch/429745/?series=89269&rev=2
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10829>

diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index 15a1b8f..43eb469 100644 (file)
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -1094,6 +1094,7 @@ to upconvert to 32b float internally?
        <reg32 offset="0x098D" name="CP_AHB_CNTL"/>
        <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST"/>
        <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD"/>
+       <reg32 offset="0x0B34" name="CP_LPAC_PROG_FIFO_SIZE"/>
        <reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
        <reg32 offset="0x0201" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK"/>
        <reg32 offset="0x0210" name="RBBM_STATUS">
@@ -1378,6 +1379,8 @@ to upconvert to 32b float internally?
                <bitfield high="7" low="0" name="PERFSEL"/>
        </reg32>
        <array offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL" stride="1" length="12"/>
+       <reg32 offset="0x0e3c" name="UCHE_CMDQ_CONFIG"/>
+
        <reg32 offset="0x3000" name="VBIF_VERSION"/>
        <reg32 offset="0x3001" name="VBIF_CLKON">
                <bitfield pos="1" name="FORCE_ON_TESTBUS" type="boolean"/>
@@ -1417,6 +1420,7 @@ to upconvert to 32b float internally?
        <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
        <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
 
+       <reg32 offset="0x3c01" name="GBIF_SCACHE_CNTL0"/>
        <reg32 offset="0x3c02" name="GBIF_SCACHE_CNTL1"/>
        <reg32 offset="0x3c03" name="GBIF_QSB_SIDE0"/>
        <reg32 offset="0x3c04" name="GBIF_QSB_SIDE1"/>

diff --git a/src/freedreno/registers/adreno/a6xx_gmu.xml b/src/freedreno/registers/adreno/a6xx_gmu.xml
index dbefd0c..f8bf1fd 100644 (file)
--- a/src/freedreno/registers/adreno/a6xx_gmu.xml
+++ b/src/freedreno/registers/adreno/a6xx_gmu.xml
@@ -112,6 +112,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
        <reg32 offset="0x50e9" name="GMU_RPMH_HYST_CTRL"/>
        <reg32 offset="0x50ec" name="GPU_GMU_CX_GMU_RPMH_POWER_STATE"/>
        <reg32 offset="0x50f0" name="GPU_GMU_CX_GMU_CX_FAL_INTF"/>
+       <reg32 offset="0x50f1" name="GPU_GMU_CX_GMU_CX_FALNEXT_INTF"/>
        <reg32 offset="0x5100" name="GPU_GMU_CX_GMU_PWR_COL_CP_MSG"/>
        <reg32 offset="0x5101" name="GPU_GMU_CX_GMU_PWR_COL_CP_RESP"/>
        <reg32 offset="0x51f0" name="GMU_BOOT_KMD_LM_HANDSHAKE"/>
@@ -193,6 +194,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
        <reg32 offset="0x9312" name="GMU_AHB_FENCE_RANGE_1"/>
        <reg32 offset="0x9c03" name="GPU_CC_GX_GDSCR"/>
        <reg32 offset="0x9d42" name="GPU_CC_GX_DOMAIN_MISC"/>
+       <reg32 offset="0xc001" name="GPU_CPR_FSM_CTL"/>
 
        <!-- starts at offset 0x8c00 on most gpus -->
        <reg32 offset="0x0004" name="GPU_RSCC_RSC_STATUS0_DRV0"/>