arm64: dts: mt7622: add cpufreq related device nodes

Add clocks, regulators and opp information into cpu nodes.
In addition, the power supply for cpu nodes is deployed on
mt7622-rfb1 board.

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
index 42bd3a4c9a9303a2ee3a5092ebe59a0fc01a6725..b3878656475cd136b1de8b43aca7b655f9245156 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -20,6 +20,18 @@
                bootargs = "console=ttyS0,115200n1";
        };
 
+       cpus {
+               cpu@0 {
+                       proc-supply = <&mt6380_vcpu_reg>;
+                       sram-supply = <&mt6380_vm_reg>;
+               };
+
+               cpu@1 {
+                       proc-supply = <&mt6380_vcpu_reg>;
+                       sram-supply = <&mt6380_vm_reg>;
+               };
+       };
+
        gpio-keys {
                compatible = "gpio-keys-polled";
                poll-interval = <100>;

diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index 2f6b88a98f4c4bdd48b41926fb998ff91a3db957..b4e5d49f919309f55a9ff7558312367758a1cb94 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -18,6 +18,50 @@
        #address-cells = <2>;
        #size-cells = <2>;
 
+       cpu_opp_table: opp-table {
+               compatible = "operating-points-v2";
+               opp-shared;
+               opp-300000000 {
+                       opp-hz = /bits/ 64 <30000000>;
+                       opp-microvolt = <950000>;
+               };
+
+               opp-437500000 {
+                       opp-hz = /bits/ 64 <437500000>;
+                       opp-microvolt = <1000000>;
+               };
+
+               opp-600000000 {
+                       opp-hz = /bits/ 64 <600000000>;
+                       opp-microvolt = <1050000>;
+               };
+
+               opp-812500000 {
+                       opp-hz = /bits/ 64 <812500000>;
+                       opp-microvolt = <1100000>;
+               };
+
+               opp-1025000000 {
+                       opp-hz = /bits/ 64 <1025000000>;
+                       opp-microvolt = <1150000>;
+               };
+
+               opp-1137500000 {
+                       opp-hz = /bits/ 64 <1137500000>;
+                       opp-microvolt = <1200000>;
+               };
+
+               opp-1262500000 {
+                       opp-hz = /bits/ 64 <1262500000>;
+                       opp-microvolt = <1250000>;
+               };
+
+               opp-1350000000 {
+                       opp-hz = /bits/ 64 <1350000000>;
+                       opp-microvolt = <1310000>;
+               };
+       };
+
        cpus {
                #address-cells = <2>;
                #size-cells = <0>;
@@ -26,6 +70,10 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x0>;
+                       clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
+                                <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
+                       clock-names = "cpu", "intermediate";
+                       operating-points-v2 = <&cpu_opp_table>;
                        enable-method = "psci";
                        clock-frequency = <1300000000>;
                };
@@ -34,6 +82,10 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x1>;
+                       clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
+                                <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
+                       clock-names = "cpu", "intermediate";
+                       operating-points-v2 = <&cpu_opp_table>;
                        enable-method = "psci";
                        clock-frequency = <1300000000>;
                };