MIPS: Add set/clear CP0 macros for PageGrain register

Build set and clear macros for the PageGrain register.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9289/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 0634600..235469a 100644 (file)
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1897,6 +1897,7 @@ __BUILD_SET_C0(config5)
 __BUILD_SET_C0(intcontrol)
 __BUILD_SET_C0(intctl)
 __BUILD_SET_C0(srsmap)
+__BUILD_SET_C0(pagegrain)
 __BUILD_SET_C0(brcm_config_0)
 __BUILD_SET_C0(brcm_bus_pll)
 __BUILD_SET_C0(brcm_reset)

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 81f0aed..48dfb9d 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -550,7 +550,7 @@ static void decode_configs(struct cpuinfo_mips *c)
 
        if (cpu_has_rixi) {
                /* Enable the RIXI exceptions */
-               write_c0_pagegrain(read_c0_pagegrain() | PG_IEC);
+               set_c0_pagegrain(PG_IEC);
                back_to_back_c0_hazard();
                /* Verify the IEC bit is set */
                if (read_c0_pagegrain() & PG_IEC)

diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index e90b2e8..b2afa49 100644 (file)
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -485,11 +485,11 @@ static void r4k_tlb_configure(void)
                 * Enable the no read, no exec bits, and enable large virtual
                 * address.
                 */
-               u32 pg = PG_RIE | PG_XIE;
 #ifdef CONFIG_64BIT
-               pg |= PG_ELPA;
+               set_c0_pagegrain(PG_RIE | PG_XIE | PG_ELPA);
+#else
+               set_c0_pagegrain(PG_RIE | PG_XIE);
 #endif
-               write_c0_pagegrain(pg);
        }
 
        temp_tlb_entry = current_cpu_data.tlbsize - 1;