spi: spi-mxs: Don't set clock for each xfer

mxs_spi_setup_transfer() would set the SSP SCK rate every time it was
called, which is before every transfer.  It is uncommon for the SCK rate to
change between transfers (or at all of that matter) and this causes many
unnecessary reprogrammings of the clock registers.

Code changed to only set the rate when it changes.  This significantly
speeds up short SPI messages, especially messages made up of many transfers,
as the calculation of the clock divisors is rather costly.  On an iMX287,
using spidev with messages that consist of 511 transfers of 4 bytes each at
an SCK of 48 MHz, the effective transfer rate more than doubles from about
290 KB/sec to 600 KB/sec!

Signed-off-by: Trent Piepho <tpiepho@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mark Brown <broonie@linaro.org>

diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
index 9e6101a..759de70 100644 (file)
--- a/drivers/spi/spi-mxs.c
+++ b/drivers/spi/spi-mxs.c
@@ -67,6 +67,7 @@
 struct mxs_spi {
        struct mxs_ssp          ssp;
        struct completion       c;
+       unsigned int            sck;    /* Rate requested (vs actual) */
 };
 
 static int mxs_spi_setup_transfer(struct spi_device *dev,
@@ -81,7 +82,19 @@ static int mxs_spi_setup_transfer(struct spi_device *dev,
                return -EINVAL;
        }
 
-       mxs_ssp_set_clk_rate(ssp, hz);
+       if (hz != spi->sck) {
+               mxs_ssp_set_clk_rate(ssp, hz);
+               /*
+                * Save requested rate, hz, rather than the actual rate,
+                * ssp->clk_rate.  Otherwise we would set the rate every trasfer
+                * when the actual rate is not quite the same as requested rate.
+                */
+               spi->sck = hz;
+               /*
+                * Perhaps we should return an error if the actual clock is
+                * nowhere close to what was requested?
+                */
+       }
 
        writel(BM_SSP_CTRL0_LOCK_CS,
                ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);