ARM64: dts: meson-axg: add saradc support

Add the DT info for SAR ADC of the Amlogic's Meson-AXG SoC.

Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 346e3b0..da84bc8 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -215,3 +215,8 @@
                compatible = "brcm,bcm4329-fmac";
        };
 };
+
+&saradc {
+       status = "okay";
+       vref-supply = <&vddio_ao18>;
+};

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index e11fec2..5f4d49e 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -91,6 +91,13 @@
                method = "smc";
        };
 
+       vddio_ao18: regulator-vddio_ao18 {
+               compatible = "regulator-fixed";
+               regulator-name = "VDDIO_AO18";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+       };
+
        timer {
                compatible = "arm,armv8-timer";
                interrupts = <GIC_PPI 13
@@ -1236,6 +1243,20 @@
                                interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
                                status = "disabled";
                        };
+
+                       saradc: adc@9000 {
+                               compatible = "amlogic,meson-axg-saradc",
+                                       "amlogic,meson-saradc";
+                               reg = <0x0 0x9000 0x0 0x38>;
+                               #io-channel-cells = <1>;
+                               interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
+                               clocks = <&xtal>,
+                                       <&clkc_AO CLKID_AO_SAR_ADC>,
+                                       <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
+                                       <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
+                               clock-names = "clkin", "core", "adc_clk", "adc_sel";
+                               status = "disabled";
+                       };
                };
        };
 };