RISC-V: Add vwmacc vv C++ api tests

gcc/testsuite/ChangeLog:

	* g++.target/riscv/rvv/base/vwmacc_vv-1.C: New test.
	* g++.target/riscv/rvv/base/vwmacc_vv-2.C: New test.
	* g++.target/riscv/rvv/base/vwmacc_vv-3.C: New test.
	* g++.target/riscv/rvv/base/vwmacc_vv_mu-1.C: New test.
	* g++.target/riscv/rvv/base/vwmacc_vv_mu-2.C: New test.
	* g++.target/riscv/rvv/base/vwmacc_vv_mu-3.C: New test.
	* g++.target/riscv/rvv/base/vwmacc_vv_tu-1.C: New test.
	* g++.target/riscv/rvv/base/vwmacc_vv_tu-2.C: New test.
	* g++.target/riscv/rvv/base/vwmacc_vv_tu-3.C: New test.
	* g++.target/riscv/rvv/base/vwmacc_vv_tum-1.C: New test.
	* g++.target/riscv/rvv/base/vwmacc_vv_tum-2.C: New test.
	* g++.target/riscv/rvv/base/vwmacc_vv_tum-3.C: New test.
	* g++.target/riscv/rvv/base/vwmacc_vv_tumu-1.C: New test.
	* g++.target/riscv/rvv/base/vwmacc_vv_tumu-2.C: New test.
	* g++.target/riscv/rvv/base/vwmacc_vv_tumu-3.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vv-1.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vv-2.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vv-3.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vv_mu-1.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vv_mu-2.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vv_mu-3.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vv_tu-1.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vv_tu-2.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vv_tu-3.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vv_tum-1.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vv_tum-2.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vv_tum-3.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.C: New test.
	* g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vv-1.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vv-2.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vv-3.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vv_mu-1.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vv_mu-2.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vv_mu-3.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vv_tu-1.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vv_tu-2.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vv_tu-3.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vv_tum-1.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vv_tum-2.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vv_tum-3.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vv_tumu-1.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vv_tumu-2.C: New test.
	* g++.target/riscv/rvv/base/vwmaccu_vv_tumu-3.C: New test.

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-1.C
new file mode 100644 (file)
index 0000000..481fe63
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-1.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmacc(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmacc(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmacc(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmacc(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmacc(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmacc(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmacc(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmacc(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmacc(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmacc(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmacc(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmacc(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmacc(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmacc(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint16mf4_t test___riscv_vwmacc(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmacc(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmacc(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmacc(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmacc(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmacc(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmacc(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmacc(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmacc(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmacc(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmacc(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmacc(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmacc(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmacc(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmacc(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-2.C
new file mode 100644 (file)
index 0000000..08c16d3
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-2.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmacc(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmacc(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmacc(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmacc(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmacc(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmacc(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmacc(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmacc(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmacc(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmacc(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmacc(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmacc(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmacc(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmacc(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint16mf4_t test___riscv_vwmacc(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmacc(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmacc(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmacc(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmacc(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmacc(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmacc(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmacc(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmacc(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmacc(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmacc(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmacc(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmacc(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmacc(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmacc(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-3.C
new file mode 100644 (file)
index 0000000..870b62c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-3.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmacc(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmacc(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmacc(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmacc(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmacc(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmacc(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmacc(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmacc(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmacc(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmacc(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmacc(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmacc(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmacc(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmacc(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint16mf4_t test___riscv_vwmacc(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmacc(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmacc(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmacc(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmacc(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmacc(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmacc(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmacc(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmacc(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmacc(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmacc(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmacc(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmacc(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmacc(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmacc(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-1.C
new file mode 100644 (file)
index 0000000..4d8564b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmacc_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmacc_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmacc_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmacc_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmacc_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmacc_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmacc_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmacc_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmacc_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmacc_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmacc_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmacc_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-2.C
new file mode 100644 (file)
index 0000000..23ec15b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmacc_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmacc_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmacc_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmacc_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmacc_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmacc_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmacc_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmacc_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmacc_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmacc_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmacc_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmacc_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-3.C
new file mode 100644 (file)
index 0000000..3e16e03
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmacc_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmacc_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmacc_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmacc_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmacc_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmacc_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmacc_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmacc_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmacc_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmacc_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmacc_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmacc_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-1.C
new file mode 100644 (file)
index 0000000..397d3f0
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_tu(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_tu(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmacc_tu(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmacc_tu(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmacc_tu(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmacc_tu(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_tu(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmacc_tu(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmacc_tu(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmacc_tu(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmacc_tu(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmacc_tu(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmacc_tu(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmacc_tu(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmacc_tu(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-2.C
new file mode 100644 (file)
index 0000000..08276ad
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_tu(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_tu(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmacc_tu(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmacc_tu(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmacc_tu(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmacc_tu(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_tu(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmacc_tu(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmacc_tu(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmacc_tu(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmacc_tu(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmacc_tu(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmacc_tu(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmacc_tu(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmacc_tu(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-3.C
new file mode 100644 (file)
index 0000000..f7df4b1
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_tu(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_tu(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmacc_tu(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmacc_tu(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmacc_tu(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmacc_tu(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_tu(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmacc_tu(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmacc_tu(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmacc_tu(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmacc_tu(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmacc_tu(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmacc_tu(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmacc_tu(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmacc_tu(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-1.C
new file mode 100644 (file)
index 0000000..afed070
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmacc_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmacc_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmacc_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmacc_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmacc_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmacc_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmacc_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmacc_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmacc_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmacc_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmacc_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmacc_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-2.C
new file mode 100644 (file)
index 0000000..657b4d9
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmacc_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmacc_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmacc_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmacc_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmacc_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmacc_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmacc_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmacc_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmacc_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmacc_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmacc_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmacc_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-3.C
new file mode 100644 (file)
index 0000000..9d28777
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmacc_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmacc_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmacc_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmacc_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmacc_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmacc_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmacc_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmacc_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmacc_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmacc_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmacc_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmacc_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-1.C
new file mode 100644 (file)
index 0000000..e45bcf5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmacc_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmacc_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmacc_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmacc_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmacc_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmacc_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmacc_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmacc_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmacc_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmacc_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmacc_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmacc_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-2.C
new file mode 100644 (file)
index 0000000..d5a0123
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmacc_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmacc_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmacc_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmacc_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmacc_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmacc_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmacc_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmacc_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmacc_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmacc_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmacc_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmacc_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-3.C
new file mode 100644 (file)
index 0000000..773f709
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmacc_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmacc_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmacc_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmacc_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmacc_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmacc_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmacc_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmacc_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmacc_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmacc_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmacc_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmacc_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-1.C
new file mode 100644 (file)
index 0000000..28f5a38
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-1.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint16mf4_t test___riscv_vwmaccsu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-2.C
new file mode 100644 (file)
index 0000000..4ccbc3a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-2.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint16mf4_t test___riscv_vwmaccsu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-3.C
new file mode 100644 (file)
index 0000000..b60666b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-3.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint16mf4_t test___riscv_vwmaccsu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-1.C
new file mode 100644 (file)
index 0000000..6581508
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-2.C
new file mode 100644 (file)
index 0000000..1704a0c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-3.C
new file mode 100644 (file)
index 0000000..4107fd7
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-1.C
new file mode 100644 (file)
index 0000000..5570d27
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_tu(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_tu(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_tu(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_tu(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_tu(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_tu(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_tu(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_tu(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_tu(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_tu(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_tu(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_tu(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_tu(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_tu(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_tu(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-2.C
new file mode 100644 (file)
index 0000000..5034aa4
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_tu(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_tu(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_tu(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_tu(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_tu(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_tu(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_tu(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_tu(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_tu(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_tu(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_tu(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_tu(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_tu(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_tu(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_tu(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-3.C
new file mode 100644 (file)
index 0000000..6e0b65b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_tu(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_tu(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_tu(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_tu(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_tu(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_tu(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_tu(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_tu(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_tu(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_tu(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_tu(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_tu(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_tu(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_tu(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_tu(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-1.C
new file mode 100644 (file)
index 0000000..5c2a3a5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-2.C
new file mode 100644 (file)
index 0000000..6aaf403
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-3.C
new file mode 100644 (file)
index 0000000..fd6fc26
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.C
new file mode 100644 (file)
index 0000000..1aa27db
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.C
new file mode 100644 (file)
index 0000000..94d4b3d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.C
new file mode 100644 (file)
index 0000000..2f694ed
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-1.C
new file mode 100644 (file)
index 0000000..b2c4989
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-1.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vwmaccu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-2.C
new file mode 100644 (file)
index 0000000..c9f3e7e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-2.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint16mf4_t test___riscv_vwmaccu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-3.C
new file mode 100644 (file)
index 0000000..210311d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-3.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint16mf4_t test___riscv_vwmaccu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-1.C
new file mode 100644 (file)
index 0000000..a77d935
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_mu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_mu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_mu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-2.C
new file mode 100644 (file)
index 0000000..b2c4a79
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_mu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_mu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_mu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-3.C
new file mode 100644 (file)
index 0000000..47bf138
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_mu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_mu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_mu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-1.C
new file mode 100644 (file)
index 0000000..9470b52
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_tu(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_tu(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_tu(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_tu(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_tu(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_tu(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_tu(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_tu(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_tu(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_tu(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_tu(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_tu(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_tu(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_tu(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_tu(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-2.C
new file mode 100644 (file)
index 0000000..dacab0a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_tu(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_tu(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_tu(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_tu(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_tu(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_tu(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_tu(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_tu(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_tu(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_tu(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_tu(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_tu(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_tu(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_tu(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_tu(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-3.C
new file mode 100644 (file)
index 0000000..d31989f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_tu(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_tu(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_tu(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_tu(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_tu(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_tu(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_tu(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_tu(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_tu(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_tu(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_tu(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_tu(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_tu(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_tu(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_tu(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-1.C
new file mode 100644 (file)
index 0000000..515c6d8
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_tum(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_tum(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_tum(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-2.C
new file mode 100644 (file)
index 0000000..1aa0b33
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_tum(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_tum(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_tum(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-3.C
new file mode 100644 (file)
index 0000000..6e2bbda
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_tum(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_tum(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_tum(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-1.C
new file mode 100644 (file)
index 0000000..39aff25
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_tumu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_tumu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_tumu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-2.C
new file mode 100644 (file)
index 0000000..2f4176a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_tumu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_tumu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_tumu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-3.C
new file mode 100644 (file)
index 0000000..0fe3dff
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_tumu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_tumu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_tumu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */