; CHECK: // %bb.0:
; CHECK-NEXT: rdvl x8, #1
; CHECK-NEXT: lsr x8, x8, #4
-; CHECK-NEXT: and w9, w8, #0x1f
-; CHECK-NEXT: and w8, w8, #0xfffffffc
-; CHECK-NEXT: add w0, w9, w8
+; CHECK-NEXT: and w9, w8, #0x1c
+; CHECK-NEXT: add w0, w8, w9
; CHECK-NEXT: ret
%vscale = call i32 @llvm.vscale.i32()
%and_redundant = and i32 %vscale, 31
; CHECK-LABEL: vscale_trunc_zext:
; CHECK: // %bb.0:
; CHECK-NEXT: rdvl x8, #1
-; CHECK-NEXT: lsr x8, x8, #4
-; CHECK-NEXT: and x0, x8, #0xffffffff
+; CHECK-NEXT: lsr x0, x8, #4
; CHECK-NEXT: ret
%vscale = call i32 @llvm.vscale.i32()
%zext = zext i32 %vscale to i64
; CHECK-LABEL: vscale_trunc_sext:
; CHECK: // %bb.0:
; CHECK-NEXT: rdvl x8, #1
-; CHECK-NEXT: lsr x8, x8, #4
-; CHECK-NEXT: sxtw x0, w8
+; CHECK-NEXT: lsr x0, x8, #4
; CHECK-NEXT: ret
%vscale = call i32 @llvm.vscale.i32()
%sext = sext i32 %vscale to i64
; CHECK-NEXT: mov w9, #5
; CHECK-NEXT: lsr x8, x8, #4
; CHECK-NEXT: mul x8, x8, x9
-; CHECK-NEXT: and w9, w8, #0x7f
-; CHECK-NEXT: and w8, w8, #0x3f
-; CHECK-NEXT: add w0, w9, w8
+; CHECK-NEXT: and w9, w8, #0x3f
+; CHECK-NEXT: add w0, w8, w9
; CHECK-NEXT: ret
%vscale = call i32 @llvm.vscale.i32()
%mul = mul i32 %vscale, 5
; CHECK-NEXT: mov x9, #-5
; CHECK-NEXT: lsr x8, x8, #4
; CHECK-NEXT: mul x8, x8, x9
-; CHECK-NEXT: orr w9, w8, #0xffffff80
-; CHECK-NEXT: and w8, w8, #0xffffffc0
-; CHECK-NEXT: add w0, w9, w8
+; CHECK-NEXT: and w9, w8, #0xffffffc0
+; CHECK-NEXT: add w0, w8, w9
; CHECK-NEXT: ret
%vscale = call i32 @llvm.vscale.i32()
%mul = mul i32 %vscale, -5
ret i32 %result
}
+define i32 @pow2_vscale_with_negative_multiplier() vscale_range(1,16) {
+; CHECK-LABEL: pow2_vscale_with_negative_multiplier:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cntd x8
+; CHECK-NEXT: neg x8, x8
+; CHECK-NEXT: orr w9, w8, #0xfffffff0
+; CHECK-NEXT: add w0, w8, w9
+; CHECK-NEXT: ret
+ %vscale = call i32 @llvm.vscale.i32()
+ %mul = mul i32 %vscale, -2
+ %or_redundant = or i32 %mul, 4294967264
+ %or_required = or i32 %mul, 4294967280
+ %result = add i32 %or_redundant, %or_required
+ ret i32 %result
+}
+
declare i32 @llvm.vscale.i32()
declare i64 @llvm.aarch64.sve.cntb(i32 %pattern)
declare i64 @llvm.aarch64.sve.cnth(i32 %pattern)
--- /dev/null
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple riscv64 -mattr +v -filetype asm -o - %s | FileCheck %s
+
+declare i8 @llvm.vscale.i8()
+declare <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8()
+
+define <vscale x 8 x i8> @f() #0 {
+; CHECK-LABEL: f:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vadd.vx v8, v8, a0
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call i8 @llvm.vscale.i8()
+ %1 = shl i8 %0, 3
+ %.splat.insert = insertelement <vscale x 8 x i8> poison, i8 %1, i64 0
+ %.splat = shufflevector <vscale x 8 x i8> %.splat.insert, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
+ %2 = tail call <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8()
+ %3 = add <vscale x 8 x i8> %2, %.splat
+ ret <vscale x 8 x i8> %3
+}
+
+attributes #0 = { vscale_range(2,1024) }