void
iris_blorp_surf_for_resource(struct iris_vtable *vtbl,
+ struct isl_device *isl_dev,
struct blorp_surf *surf,
struct pipe_resource *p_res,
enum isl_aux_usage aux_usage,
.buffer = res->bo,
.offset = res->offset,
.reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0,
- .mocs = vtbl->mocs(res->bo),
+ .mocs = vtbl->mocs(res->bo, isl_dev),
},
.aux_usage = aux_usage,
};
.buffer = res->aux.bo,
.offset = res->aux.offset,
.reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0,
- .mocs = vtbl->mocs(res->bo),
+ .mocs = vtbl->mocs(res->bo, isl_dev),
};
surf->clear_color =
iris_resource_get_clear_color(res, NULL, NULL);
.buffer = res->aux.clear_color_bo,
.offset = res->aux.clear_color_offset,
.reloc_flags = 0,
- .mocs = vtbl->mocs(res->aux.clear_color_bo),
+ .mocs = vtbl->mocs(res->aux.clear_color_bo, isl_dev),
};
}
bool dst_clear_supported = dst_aux_usage != ISL_AUX_USAGE_NONE;
struct blorp_surf src_surf, dst_surf;
- iris_blorp_surf_for_resource(&ice->vtbl, &src_surf, info->src.resource,
- src_aux_usage, info->src.level, false);
- iris_blorp_surf_for_resource(&ice->vtbl, &dst_surf, info->dst.resource,
- dst_aux_usage, info->dst.level, true);
+ iris_blorp_surf_for_resource(&ice->vtbl, &screen->isl_dev, &src_surf,
+ info->src.resource, src_aux_usage,
+ info->src.level, false);
+ iris_blorp_surf_for_resource(&ice->vtbl, &screen->isl_dev, &dst_surf,
+ info->dst.resource, dst_aux_usage,
+ info->dst.level, true);
iris_resource_prepare_access(ice, batch, dst_res, info->dst.level, 1,
info->dst.box.z, info->dst.box.depth,
iris_resource_prepare_access(ice, batch, stc_dst, info->dst.level, 1,
info->dst.box.z, info->dst.box.depth,
stc_dst_aux_usage, false);
- iris_blorp_surf_for_resource(&ice->vtbl, &src_surf, &src_res->base,
- stc_src_aux_usage, info->src.level, false);
- iris_blorp_surf_for_resource(&ice->vtbl, &dst_surf, &stc_dst->base,
- stc_dst_aux_usage, info->dst.level, true);
+ iris_blorp_surf_for_resource(&ice->vtbl, &screen->isl_dev, &src_surf,
+ &src_res->base, stc_src_aux_usage,
+ info->src.level, false);
+ iris_blorp_surf_for_resource(&ice->vtbl, &screen->isl_dev, &dst_surf,
+ &stc_dst->base, stc_dst_aux_usage,
+ info->dst.level, true);
for (int slice = 0; slice < info->dst.box.depth; slice++) {
iris_batch_maybe_flush(batch, 1500);
// XXX: what about one surface being a buffer and not the other?
struct blorp_surf src_surf, dst_surf;
- iris_blorp_surf_for_resource(&ice->vtbl, &src_surf, src, src_aux_usage,
- src_level, false);
- iris_blorp_surf_for_resource(&ice->vtbl, &dst_surf, dst, dst_aux_usage,
- dst_level, true);
+ iris_blorp_surf_for_resource(&ice->vtbl, &screen->isl_dev, &src_surf,
+ src, src_aux_usage, src_level, false);
+ iris_blorp_surf_for_resource(&ice->vtbl, &screen->isl_dev, &dst_surf,
+ dst, dst_aux_usage, dst_level, true);
iris_resource_prepare_access(ice, batch, src_res, src_level, 1,
src_box->z, src_box->depth,
blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags);
struct blorp_surf surf;
- iris_blorp_surf_for_resource(&ice->vtbl, &surf, p_res, res->aux.usage,
- level, true);
+ iris_blorp_surf_for_resource(&ice->vtbl, &batch->screen->isl_dev, &surf,
+ p_res, res->aux.usage, level, true);
/* In newer gens (> 9), the hardware will do a linear -> sRGB conversion of
* the clear color during the fast clear, if the surface format is of sRGB
box->z, box->depth, aux_usage);
struct blorp_surf surf;
- iris_blorp_surf_for_resource(&ice->vtbl, &surf, p_res, aux_usage, level,
- true);
+ iris_blorp_surf_for_resource(&ice->vtbl, &batch->screen->isl_dev, &surf,
+ p_res, aux_usage, level, true);
struct blorp_batch blorp_batch;
blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags);
if (clear_depth && z_res) {
iris_resource_prepare_depth(ice, batch, z_res, level, box->z, box->depth);
- iris_blorp_surf_for_resource(&ice->vtbl, &z_surf, &z_res->base,
- z_res->aux.usage, level, true);
+ iris_blorp_surf_for_resource(&ice->vtbl, &batch->screen->isl_dev,
+ &z_surf, &z_res->base, z_res->aux.usage,
+ level, true);
}
struct blorp_batch blorp_batch;
if (stencil_mask) {
iris_resource_prepare_access(ice, batch, stencil_res, level, 1, box->z,
box->depth, stencil_res->aux.usage, false);
- iris_blorp_surf_for_resource(&ice->vtbl, &stencil_surf,
- &stencil_res->base, stencil_res->aux.usage,
- level, true);
+ iris_blorp_surf_for_resource(&ice->vtbl, &batch->screen->isl_dev,
+ &stencil_surf, &stencil_res->base,
+ stencil_res->aux.usage, level, true);
}
blorp_clear_depth_stencil(&blorp_batch, &z_surf, &stencil_surf,
struct brw_wm_prog_key *key);
void (*populate_cs_key)(const struct iris_context *ice,
struct brw_cs_prog_key *key);
- uint32_t (*mocs)(const struct iris_bo *bo);
+ uint32_t (*mocs)(const struct iris_bo *bo, const struct isl_device *isl_dev);
void (*lost_genx_state)(struct iris_context *ice, struct iris_batch *batch);
};
/* iris_blit.c */
void iris_blorp_surf_for_resource(struct iris_vtable *vtbl,
+ struct isl_device *isl_dev,
struct blorp_surf *surf,
struct pipe_resource *p_res,
enum isl_aux_usage aux_usage,
.size_B = sizeof(grid->grid),
.format = ISL_FORMAT_RAW,
.stride_B = 1,
- .mocs = ice->vtbl.mocs(grid_bo));
+ .mocs = ice->vtbl.mocs(grid_bo, isl_dev));
ice->state.dirty |= IRIS_DIRTY_BINDINGS_CS;
}
: ISL_FORMAT_R32G32B32A32_FLOAT,
.swizzle = ISL_SWIZZLE_IDENTITY,
.stride_B = 1,
- .mocs = ice->vtbl.mocs(res->bo));
+ .mocs = ice->vtbl.mocs(res->bo, &screen->isl_dev));
}
static nir_ssa_def *
//DBG("%s to mt %p level %u layer %u\n", __FUNCTION__, mt, level, layer);
struct blorp_surf surf;
- iris_blorp_surf_for_resource(&ice->vtbl, &surf, &res->base, res->aux.usage,
- level, true);
+ iris_blorp_surf_for_resource(&ice->vtbl, &batch->screen->isl_dev, &surf,
+ &res->base, res->aux.usage, level, true);
iris_batch_maybe_flush(batch, 1500);
assert(isl_aux_usage_has_mcs(res->aux.usage));
struct blorp_surf surf;
- iris_blorp_surf_for_resource(&ice->vtbl, &surf, &res->base, res->aux.usage,
- 0, true);
+ iris_blorp_surf_for_resource(&ice->vtbl, &batch->screen->isl_dev, &surf,
+ &res->base, res->aux.usage, 0, true);
struct blorp_batch blorp_batch;
blorp_batch_init(&ice->blorp, &blorp_batch, batch, 0);
iris_batch_maybe_flush(batch, 1500);
struct blorp_surf surf;
- iris_blorp_surf_for_resource(&ice->vtbl, &surf, &res->base,
- res->aux.usage, level, true);
+ iris_blorp_surf_for_resource(&ice->vtbl, &batch->screen->isl_dev, &surf,
+ &res->base, res->aux.usage, level, true);
struct blorp_batch blorp_batch;
enum blorp_batch_flags flags = 0;
#include "iris_genx_macros.h"
#include "intel/common/gen_guardband.h"
-#if GEN_GEN >= 12
-/* TODO: Set PTE to MOCS 61 when the kernel is ready */
-#define MOCS_PTE (3 << 1)
-#define MOCS_WB (2 << 1)
-#elif GEN_GEN >= 9
-#define MOCS_PTE (1 << 1)
-#define MOCS_WB (2 << 1)
-#elif GEN_GEN == 8
-#define MOCS_PTE 0x18
-#define MOCS_WB 0x78
-#endif
-
static uint32_t
-mocs(const struct iris_bo *bo)
+mocs(const struct iris_bo *bo, const struct isl_device *dev)
{
- return bo && bo->external ? MOCS_PTE : MOCS_WB;
+ return bo && bo->external ? dev->mocs.external : dev->mocs.internal;
}
/**
static void
init_state_base_address(struct iris_batch *batch)
{
+ uint32_t mocs = batch->screen->isl_dev.mocs.internal;
flush_before_state_base_change(batch);
/* We program most base addresses once at context initialization time.
* updated occasionally. See iris_binder.c for the details there.
*/
iris_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) {
- sba.GeneralStateMOCS = MOCS_WB;
- sba.StatelessDataPortAccessMOCS = MOCS_WB;
- sba.DynamicStateMOCS = MOCS_WB;
- sba.IndirectObjectMOCS = MOCS_WB;
- sba.InstructionMOCS = MOCS_WB;
- sba.SurfaceStateMOCS = MOCS_WB;
+ sba.GeneralStateMOCS = mocs;
+ sba.StatelessDataPortAccessMOCS = mocs;
+ sba.DynamicStateMOCS = mocs;
+ sba.IndirectObjectMOCS = mocs;
+ sba.InstructionMOCS = mocs;
+ sba.SurfaceStateMOCS = mocs;
sba.GeneralStateBaseAddressModifyEnable = true;
sba.DynamicStateBaseAddressModifyEnable = true;
sba.DynamicStateBufferSizeModifyEnable = true;
#if (GEN_GEN >= 9)
sba.BindlessSurfaceStateBaseAddressModifyEnable = true;
- sba.BindlessSurfaceStateMOCS = MOCS_WB;
+ sba.BindlessSurfaceStateMOCS = mocs;
#endif
sba.IndirectObjectBufferSizeModifyEnable = true;
sba.InstructionBuffersizeModifyEnable = true;
.format = format,
.swizzle = swizzle,
.stride_B = cpp,
- .mocs = mocs(res->bo));
+ .mocs = mocs(res->bo, isl_dev));
}
#define SURFACE_STATE_ALIGNMENT 64
struct isl_surf_fill_state_info f = {
.surf = surf,
.view = view,
- .mocs = mocs(res->bo),
+ .mocs = mocs(res->bo, isl_dev),
.address = res->bo->gtt_offset + res->offset,
.x_offset_sa = tile_x_sa,
.y_offset_sa = tile_y_sa,
struct isl_surf_fill_state_info f = {
.surf = &isl_surf,
.view = view,
- .mocs = mocs(res->bo),
+ .mocs = mocs(res->bo, &screen->isl_dev),
.address = res->bo->gtt_offset + offset_B,
.x_offset_sa = tile_x_sa,
.y_offset_sa = tile_y_sa,
info.depth_surf = &zres->surf;
info.depth_address = zres->bo->gtt_offset + zres->offset;
- info.mocs = mocs(zres->bo);
+ info.mocs = mocs(zres->bo, isl_dev);
view.format = zres->surf.format;
info.stencil_address = stencil_res->bo->gtt_offset + stencil_res->offset;
if (!zres) {
view.format = stencil_res->surf.format;
- info.mocs = mocs(stencil_res->bo);
+ info.mocs = mocs(stencil_res->bo, isl_dev);
}
}
}
const struct pipe_vertex_buffer *buffers)
{
struct iris_context *ice = (struct iris_context *) ctx;
+ struct iris_screen *screen = (struct iris_screen *)ctx->screen;
struct iris_genx_state *genx = ice->state.genx;
ice->state.bound_vertex_buffers &= ~u_bit_consecutive64(start_slot, count);
vb.BufferSize = res->bo->size - (int) buffer->buffer_offset;
vb.BufferStartingAddress =
ro_bo(NULL, res->bo->gtt_offset + (int) buffer->buffer_offset);
- vb.MOCS = mocs(res->bo);
+ vb.MOCS = mocs(res->bo, &screen->isl_dev);
} else {
vb.NullVertexBuffer = true;
}
struct iris_context *ice = (struct iris_context *) ctx;
struct iris_genx_state *genx = ice->state.genx;
uint32_t *so_buffers = genx->so_buffers;
+ struct iris_screen *screen = (struct iris_screen *)ctx->screen;
const bool active = num_targets > 0;
if (ice->state.streamout_active != active) {
sob.SOBufferEnable = true;
sob.StreamOffsetWriteEnable = true;
sob.StreamOutputBufferOffsetAddressEnable = true;
- sob.MOCS = mocs(res->bo);
+ sob.MOCS = mocs(res->bo, &screen->isl_dev);
sob.SurfaceSize = MAX2(tgt->base.buffer_size / 4, 1) - 1;
sob.StreamOffset = offset;
if (batch->last_surface_base_address == binder->bo->gtt_offset)
return;
+ uint32_t mocs = batch->screen->isl_dev.mocs.internal;
+
flush_before_state_base_change(batch);
iris_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) {
/* The hardware appears to pay attention to the MOCS fields even
* if you don't set the "Address Modify Enable" bit for the base.
*/
- sba.GeneralStateMOCS = MOCS_WB;
- sba.StatelessDataPortAccessMOCS = MOCS_WB;
- sba.DynamicStateMOCS = MOCS_WB;
- sba.IndirectObjectMOCS = MOCS_WB;
- sba.InstructionMOCS = MOCS_WB;
- sba.SurfaceStateMOCS = MOCS_WB;
+ sba.GeneralStateMOCS = mocs;
+ sba.StatelessDataPortAccessMOCS = mocs;
+ sba.DynamicStateMOCS = mocs;
+ sba.IndirectObjectMOCS = mocs;
+ sba.InstructionMOCS = mocs;
+ sba.SurfaceStateMOCS = mocs;
#if GEN_GEN >= 9
- sba.BindlessSurfaceStateMOCS = MOCS_WB;
+ sba.BindlessSurfaceStateMOCS = mocs;
#endif
}
vb.BufferStartingAddress =
ro_bo(NULL, res->bo->gtt_offset +
(int) ice->draw.draw_params.offset);
- vb.MOCS = mocs(res->bo);
+ vb.MOCS = mocs(res->bo, &batch->screen->isl_dev);
}
dynamic_bound |= 1ull << count;
count++;
vb.BufferStartingAddress =
ro_bo(NULL, res->bo->gtt_offset +
(int) ice->draw.derived_draw_params.offset);
- vb.MOCS = mocs(res->bo);
+ vb.MOCS = mocs(res->bo, &batch->screen->isl_dev);
}
dynamic_bound |= 1ull << count;
count++;
uint32_t ib_packet[GENX(3DSTATE_INDEX_BUFFER_length)];
iris_pack_command(GENX(3DSTATE_INDEX_BUFFER), ib_packet, ib) {
ib.IndexFormat = draw->index_size >> 1;
- ib.MOCS = mocs(bo);
+ ib.MOCS = mocs(bo, &batch->screen->isl_dev);
ib.BufferSize = bo->size - offset;
ib.BufferStartingAddress = ro_bo(NULL, bo->gtt_offset + offset);
}