#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
/* Flag that CPU access will not work, this VRAM domain is invisible */
#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
-/* Flag that un-cached attributes should be used for GTT */
-#define AMDGPU_GEM_CREATE_CPU_GTT_UC (1 << 2)
/* Flag that USWC attributes should be used for GTT */
-#define AMDGPU_GEM_CREATE_CPU_GTT_WC (1 << 3)
+#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
/* Flag mask for GTT domain_flags */
#define AMDGPU_GEM_CREATE_CPU_GTT_MASK \
- (AMDGPU_GEM_CREATE_CPU_GTT_WC | \
- AMDGPU_GEM_CREATE_CPU_GTT_UC | \
+ (AMDGPU_GEM_CREATE_CPU_GTT_USWC | \
AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | \
AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
bo = gpu_mem_alloc(device_handle,
4096, 4096,
AMDGPU_GEM_DOMAIN_GTT,
- AMDGPU_GEM_CREATE_CPU_GTT_WC,
+ AMDGPU_GEM_CREATE_CPU_GTT_USWC,
&bo_mc);
r = amdgpu_bo_free(bo);
uint64_t bo_mc;
volatile uint32_t *bo_cpu;
int i, j, r, loop;
- uint64_t gtt_flags[3] = {0, AMDGPU_GEM_CREATE_CPU_GTT_UC,
- AMDGPU_GEM_CREATE_CPU_GTT_WC};
+ uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC};
pm4 = calloc(pm4_dw, sizeof(*pm4));
CU_ASSERT_NOT_EQUAL(pm4, NULL);
CU_ASSERT_NOT_EQUAL(resources, NULL);
loop = 0;
- while(loop < 3) {
+ while(loop < 2) {
/* allocate UC bo for sDMA use */
bo = gpu_mem_alloc(device_handle,
sdma_write_length * sizeof(uint32_t),
uint64_t bo_mc;
volatile uint32_t *bo_cpu;
int i, j, r, loop;
- uint64_t gtt_flags[3] = {0, AMDGPU_GEM_CREATE_CPU_GTT_UC,
- AMDGPU_GEM_CREATE_CPU_GTT_WC};
+ uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC};
pm4 = calloc(pm4_dw, sizeof(*pm4));
CU_ASSERT_NOT_EQUAL(pm4, NULL);
CU_ASSERT_NOT_EQUAL(resources, NULL);
loop = 0;
- while(loop < 3) {
+ while(loop < 2) {
/* allocate UC bo for sDMA use */
bo = gpu_mem_alloc(device_handle,
sdma_write_length, 4096,
uint64_t bo1_mc, bo2_mc;
volatile unsigned char *bo1_cpu, *bo2_cpu;
int i, j, r, loop1, loop2;
- uint64_t gtt_flags[3] = {0, AMDGPU_GEM_CREATE_CPU_GTT_UC,
- AMDGPU_GEM_CREATE_CPU_GTT_WC};
+ uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC};
pm4 = calloc(pm4_dw, sizeof(*pm4));
CU_ASSERT_NOT_EQUAL(pm4, NULL);
loop1 = loop2 = 0;
/* run 9 circle to test all mapping combination */
- while(loop1 < 3) {
- while(loop2 < 3) {
+ while(loop1 < 2) {
+ while(loop2 < 2) {
/* allocate UC bo1for sDMA use */
bo1 = gpu_mem_alloc(device_handle,
sdma_write_length, 4096,