[ARM64] genSIMDIntrinsicInit contain 0
authorSteve MacLean <sdmaclea.qdt@qualcommdatacenter.com>
Fri, 10 Nov 2017 17:57:21 +0000 (12:57 -0500)
committerSteve MacLean <sdmaclea.qdt@qualcommdatacenter.com>
Fri, 10 Nov 2017 18:49:57 +0000 (13:49 -0500)
src/jit/codegenarm64.cpp
src/jit/lowerarmarch.cpp
src/jit/lsraarm64.cpp

index f507ceb..69b8598 100644 (file)
@@ -4051,13 +4051,12 @@ void CodeGen::genSIMDIntrinsicInit(GenTreeSIMD* simdNode)
     var_types targetType = simdNode->TypeGet();
 
     genConsumeOperands(simdNode);
-    regNumber op1Reg = op1->gtRegNum;
+    regNumber op1Reg = op1->IsIntegralConst(0) ? REG_ZR : op1->gtRegNum;
 
-    // TODO-ARM64-CQ Add support contain int const zero
     // TODO-ARM64-CQ Add LD1R to allow SIMDIntrinsicInit from contained memory
     // TODO-ARM64-CQ Add MOVI to allow SIMDIntrinsicInit from contained immediate small constants
 
-    assert(!op1->isContained());
+    assert(op1->isContained() == op1->IsIntegralConst(0));
     assert(!op1->isUsedFromMemory());
 
     assert(genIsValidFloatReg(targetReg));
index 6526117..ae46b54 100644 (file)
@@ -761,7 +761,11 @@ void Lowering::ContainCheckSIMD(GenTreeSIMD* simdNode)
         GenTree* op2;
 
         case SIMDIntrinsicInit:
-            // TODO-ARM64-CQ Support containing 0
+            op1 = simdNode->gtOp.gtOp1;
+            if (op1->IsIntegralConst(0))
+            {
+                MakeSrcContained(simdNode, op1);
+            }
             break;
 
         case SIMDIntrinsicInitArray:
index 346115f..8f3d034 100644 (file)
@@ -796,8 +796,11 @@ void LinearScan::TreeNodeInfoInitSIMD(GenTreeSIMD* simdTree)
         GenTree* op1;
         GenTree* op2;
 
-        case SIMDIntrinsicCast:
         case SIMDIntrinsicInit:
+            info->srcCount = simdTree->gtGetOp1()->isContained() ? 0 : 1;
+            break;
+
+        case SIMDIntrinsicCast:
         case SIMDIntrinsicSqrt:
         case SIMDIntrinsicAbs:
         case SIMDIntrinsicConvertToSingle: