Pull Rockchip clk driver updates from Heiko Stuebner:
Fix for PLL rate calculation on rk3328 and SET_RATE_PARENT flag
for the display clock on rk3066.
* tag 'v5.1-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: add CLK_SET_RATE_PARENT for rk3066 lcdc dclks
clk: rockchip: fix frac settings of GPLL clock for rk3328