ARM: dts: renesas: Move enable-method to CPU nodes

According to Documentation/devicetree/bindings/arm/cpus.yaml, the
"enable-method" property should be a property of the individual CPU
nodes, and not of the parent "cpus" container node.
However, on R-Car Gen2 and RZ/G1 SoCs, the property is tied to the
"cpus" node instead.

Secondary CPU bringup and CPU hot (un)plug work regardless, as
arm_dt_init_cpu_maps() falls back to looking in the "cpus" node.

The cpuidle code does not have such a fallback, so it does not detect
the enable-method.  Note that cpuidle does not support the
"renesas,apmu" enable-method yet, so for now this does not make any
difference.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/35fcfedf9de9269185c48ca5a6dfcba7cdd3484b.1621427319.git.geert+renesas@glider.be

diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index 8e98906..a227968 100644 (file)
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -47,7 +47,6 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
-               enable-method = "renesas,apmu";
 
                cpu0: cpu@0 {
                        device_type = "cpu";
@@ -56,6 +55,7 @@
                        clock-frequency = <1400000000>;
                        clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
                        power-domains = <&sysc R8A7742_PD_CA15_CPU0>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA15>;
                        capacity-dmips-mhz = <1024>;
                        voltage-tolerance = <1>; /* 1% */
@@ -77,6 +77,7 @@
                        clock-frequency = <1400000000>;
                        clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
                        power-domains = <&sysc R8A7742_PD_CA15_CPU1>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA15>;
                        capacity-dmips-mhz = <1024>;
                        voltage-tolerance = <1>; /* 1% */
@@ -98,6 +99,7 @@
                        clock-frequency = <1400000000>;
                        clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
                        power-domains = <&sysc R8A7742_PD_CA15_CPU2>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA15>;
                        capacity-dmips-mhz = <1024>;
                        voltage-tolerance = <1>; /* 1% */
@@ -119,6 +121,7 @@
                        clock-frequency = <1400000000>;
                        clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
                        power-domains = <&sysc R8A7742_PD_CA15_CPU3>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA15>;
                        capacity-dmips-mhz = <1024>;
                        voltage-tolerance = <1>; /* 1% */

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 16e3bf0..7e5e09d 100644 (file)
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -49,7 +49,6 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
-               enable-method = "renesas,apmu";
 
                cpu0: cpu@0 {
                        device_type = "cpu";
@@ -59,6 +58,7 @@
                        clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
                        clock-latency = <300000>; /* 300 us */
                        power-domains = <&sysc R8A7743_PD_CA15_CPU0>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA15>;
 
                        /* kHz - uV - OPPs unknown yet */
@@ -78,6 +78,7 @@
                        clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
                        clock-latency = <300000>; /* 300 us */
                        power-domains = <&sysc R8A7743_PD_CA15_CPU1>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA15>;
 
                        /* kHz - uV - OPPs unknown yet */

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 4865e39..8419683 100644 (file)
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -49,7 +49,6 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
-               enable-method = "renesas,apmu";
 
                cpu0: cpu@0 {
                        device_type = "cpu";
@@ -59,6 +58,7 @@
                        clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
                        clock-latency = <300000>; /* 300 us */
                        power-domains = <&sysc R8A7744_PD_CA15_CPU0>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA15>;
 
                        /* kHz - uV - OPPs unknown yet */
@@ -78,6 +78,7 @@
                        clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
                        clock-latency = <300000>; /* 300 us */
                        power-domains = <&sysc R8A7744_PD_CA15_CPU1>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA15>;
 
                        /* kHz - uV - OPPs unknown yet */

diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index 36892ea..f877c51 100644 (file)
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -64,7 +64,6 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
-               enable-method = "renesas,apmu";
 
                cpu0: cpu@0 {
                        device_type = "cpu";
@@ -73,6 +72,7 @@
                        clock-frequency = <1000000000>;
                        clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
                        power-domains = <&sysc R8A7745_PD_CA7_CPU0>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA7>;
                };
 
@@ -83,6 +83,7 @@
                        clock-frequency = <1000000000>;
                        clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
                        power-domains = <&sysc R8A7745_PD_CA7_CPU1>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA7>;
                };
 

diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index 5d1f357..13ef1e9 100644 (file)
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -25,7 +25,6 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
-               enable-method = "renesas,apmu";
 
                cpu0: cpu@0 {
                        device_type = "cpu";
@@ -34,6 +33,7 @@
                        clock-frequency = <1000000000>;
                        clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
                        power-domains = <&sysc R8A77470_PD_CA7_CPU0>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA7>;
                };
 
@@ -44,6 +44,7 @@
                        clock-frequency = <1000000000>;
                        clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
                        power-domains = <&sysc R8A77470_PD_CA7_CPU1>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA7>;
                };
 

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index f7c4b52..ed6dd4f 100644 (file)
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -69,7 +69,6 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
-               enable-method = "renesas,apmu";
 
                cpu0: cpu@0 {
                        device_type = "cpu";
@@ -78,6 +77,7 @@
                        clock-frequency = <1300000000>;
                        clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
                        power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA15>;
                        capacity-dmips-mhz = <1024>;
                        voltage-tolerance = <1>; /* 1% */
@@ -99,6 +99,7 @@
                        clock-frequency = <1300000000>;
                        clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
                        power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA15>;
                        capacity-dmips-mhz = <1024>;
                        voltage-tolerance = <1>; /* 1% */
@@ -120,6 +121,7 @@
                        clock-frequency = <1300000000>;
                        clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
                        power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA15>;
                        capacity-dmips-mhz = <1024>;
                        voltage-tolerance = <1>; /* 1% */
@@ -141,6 +143,7 @@
                        clock-frequency = <1300000000>;
                        clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
                        power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA15>;
                        capacity-dmips-mhz = <1024>;
                        voltage-tolerance = <1>; /* 1% */
@@ -162,6 +165,7 @@
                        clock-frequency = <780000000>;
                        clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
                        power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA7>;
                        capacity-dmips-mhz = <539>;
                };
@@ -173,6 +177,7 @@
                        clock-frequency = <780000000>;
                        clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
                        power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA7>;
                        capacity-dmips-mhz = <539>;
                };
@@ -184,6 +189,7 @@
                        clock-frequency = <780000000>;
                        clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
                        power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA7>;
                        capacity-dmips-mhz = <539>;
                };
@@ -195,6 +201,7 @@
                        clock-frequency = <780000000>;
                        clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
                        power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA7>;
                        capacity-dmips-mhz = <539>;
                };

diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index f05d754..0ccc162 100644 (file)
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -68,7 +68,6 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
-               enable-method = "renesas,apmu";
 
                cpu0: cpu@0 {
                        device_type = "cpu";
@@ -77,6 +76,7 @@
                        clock-frequency = <1500000000>;
                        clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
                        power-domains = <&sysc R8A7791_PD_CA15_CPU0>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA15>;
                        voltage-tolerance = <1>; /* 1% */
                        clock-latency = <300000>; /* 300 us */
@@ -97,6 +97,7 @@
                        clock-frequency = <1500000000>;
                        clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
                        power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA15>;
                        voltage-tolerance = <1>; /* 1% */
                        clock-latency = <300000>; /* 300 us */

diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index bd7ff20..9cdb738 100644 (file)
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -45,7 +45,6 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
-               enable-method = "renesas,apmu";
 
                cpu0: cpu@0 {
                        device_type = "cpu";
@@ -54,6 +53,7 @@
                        clock-frequency = <1000000000>;
                        clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
                        power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA15>;
                };
 
@@ -64,6 +64,7 @@
                        clock-frequency = <1000000000>;
                        clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
                        power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA15>;
                };
 

diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 6d74475..dea4b1e 100644 (file)
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -60,7 +60,6 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
-               enable-method = "renesas,apmu";
 
                cpu0: cpu@0 {
                        device_type = "cpu";
@@ -69,6 +68,7 @@
                        clock-frequency = <1500000000>;
                        clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
                        power-domains = <&sysc R8A7793_PD_CA15_CPU0>;
+                       enable-method = "renesas,apmu";
                        voltage-tolerance = <1>; /* 1% */
                        clock-latency = <300000>; /* 300 us */
 
@@ -89,6 +89,7 @@
                        clock-frequency = <1500000000>;
                        clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
                        power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
+                       enable-method = "renesas,apmu";
                        voltage-tolerance = <1>; /* 1% */
                        clock-latency = <300000>; /* 300 us */
 

diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 0035770..eac9ed8 100644 (file)
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -62,7 +62,6 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
-               enable-method = "renesas,apmu";
 
                cpu0: cpu@0 {
                        device_type = "cpu";
@@ -71,6 +70,7 @@
                        clock-frequency = <1000000000>;
                        clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
                        power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA7>;
                };
 
@@ -81,6 +81,7 @@
                        clock-frequency = <1000000000>;
                        clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
                        power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
+                       enable-method = "renesas,apmu";
                        next-level-cache = <&L2_CA7>;
                };