radeon_emit(cs, value);
}
-static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
+static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num, bool perfctr)
{
SI_CHECK_SHADOWED_REGS(reg, num);
assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
- radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0));
+ radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, perfctr));
radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
}
static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
{
- radeon_set_uconfig_reg_seq(cs, reg, 1);
+ radeon_set_uconfig_reg_seq(cs, reg, 1, false);
+ radeon_emit(cs, value);
+}
+
+static inline void radeon_set_uconfig_reg_perfctr(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
+{
+ radeon_set_uconfig_reg_seq(cs, reg, 1, true);
radeon_emit(cs, value);
}
{
struct radeon_cmdbuf *cs = &sctx->gfx_cs;
- radeon_set_uconfig_reg_seq(cs, R_036780_SQ_PERFCOUNTER_CTRL, 2);
+ radeon_set_uconfig_reg_seq(cs, R_036780_SQ_PERFCOUNTER_CTRL, 2, false);
radeon_emit(cs, shaders & 0x7f);
radeon_emit(cs, 0xffffffff);
}
dw = count + regs->num_prelude;
if (count >= regs->num_multi)
dw += regs->num_multi;
- radeon_set_uconfig_reg_seq(cs, regs->select0, dw);
+ radeon_set_uconfig_reg_seq(cs, regs->select0, dw, false);
for (idx = 0; idx < regs->num_prelude; ++idx)
radeon_emit(cs, 0);
for (idx = 0; idx < MIN2(count, regs->num_multi); ++idx)
if (count < regs->num_multi) {
unsigned select1 = regs->select0 + 4 * regs->num_multi;
- radeon_set_uconfig_reg_seq(cs, select1, count);
+ radeon_set_uconfig_reg_seq(cs, select1, count, false);
}
for (idx = 0; idx < MIN2(count, regs->num_multi); ++idx)
assert(!(regs->layout & SI_PC_REG_REVERSE));
- radeon_set_uconfig_reg_seq(cs, regs->select0, count + regs->num_prelude);
+ radeon_set_uconfig_reg_seq(cs, regs->select0, count + regs->num_prelude, false);
for (idx = 0; idx < regs->num_prelude; ++idx)
radeon_emit(cs, 0);
for (idx = 0; idx < count; ++idx)
select1 = regs->select0 + 4 * regs->num_counters;
select1_count = MIN2(count, regs->num_multi);
- radeon_set_uconfig_reg_seq(cs, select1, select1_count);
+ radeon_set_uconfig_reg_seq(cs, select1, select1_count, false);
for (idx = 0; idx < select1_count; ++idx)
radeon_emit(cs, 0);
} else if (layout_multi == SI_PC_MULTI_CUSTOM) {
reg_count += regs->num_prelude;
if (!(regs->layout & SI_PC_REG_REVERSE)) {
- radeon_set_uconfig_reg_seq(cs, reg_base, reg_count);
+ radeon_set_uconfig_reg_seq(cs, reg_base, reg_count, false);
for (idx = 0; idx < regs->num_prelude; ++idx)
radeon_emit(cs, 0);
}
} else {
reg_base -= (reg_count - 1) * 4;
- radeon_set_uconfig_reg_seq(cs, reg_base, reg_count);
+ radeon_set_uconfig_reg_seq(cs, reg_base, reg_count, false);
for (idx = count; idx > 0; --idx) {
if (idx <= regs->num_multi)