intel: add PCI IDs for Ivy Bridge GT2 server variant
authorEugeni Dodonov <eugeni.dodonov@intel.com>
Sat, 31 Mar 2012 15:38:59 +0000 (12:38 -0300)
committerEugeni Dodonov <eugeni.dodonov@intel.com>
Sun, 1 Apr 2012 13:50:55 +0000 (10:50 -0300)
Those IDs are used by Bromolow.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
include/pci_ids/i965_pci_ids.h
src/mesa/drivers/dri/intel/intel_chipset.h
src/mesa/drivers/dri/intel/intel_context.c

index a291509..e38f8d2 100644 (file)
@@ -25,6 +25,7 @@ CHIPSET(0x0162, IVYBRIDGE_GT2, ivb_gt2)
 CHIPSET(0x0156, IVYBRIDGE_M_GT1, ivb_gt1)
 CHIPSET(0x0166, IVYBRIDGE_M_GT2, ivb_gt2)
 CHIPSET(0x015a, IVYBRIDGE_S_GT1, ivb_gt1)
+CHIPSET(0x016a, IVYBRIDGE_S_GT2, ivb_gt2)
 CHIPSET(0x0402, HASWELL_GT1, hsw_gt1)
 CHIPSET(0x0412, HASWELL_GT2, hsw_gt2)
 CHIPSET(0x0406, HASWELL_M_GT1, hsw_gt1)
index 424c70c..c1d904e 100644 (file)
@@ -85,6 +85,7 @@
 #define PCI_CHIP_IVYBRIDGE_M_GT1        0x0156  /* Mobile */
 #define PCI_CHIP_IVYBRIDGE_M_GT2        0x0166
 #define PCI_CHIP_IVYBRIDGE_S_GT1        0x015a  /* Server */
+#define PCI_CHIP_IVYBRIDGE_S_GT2        0x016a
 
 #define PCI_CHIP_HASWELL_GT1            0x0402 /* Desktop */
 #define PCI_CHIP_HASWELL_GT2            0x0412
                                 devid == PCI_CHIP_IVYBRIDGE_S_GT1)
 
 #define IS_IVB_GT2(devid)       (devid == PCI_CHIP_IVYBRIDGE_GT2 || \
-                                devid == PCI_CHIP_IVYBRIDGE_M_GT2)
+                                devid == PCI_CHIP_IVYBRIDGE_M_GT2 || \
+                                devid == PCI_CHIP_IVYBRIDGE_S_GT2)
 
 #define IS_IVYBRIDGE(devid)     (IS_IVB_GT1(devid) || IS_IVB_GT2(devid))
 
index ff2b7fe..0a813a4 100644 (file)
@@ -183,6 +183,7 @@ intelGetString(struct gl_context * ctx, GLenum name)
         chipset = "Intel(R) Ivybridge Mobile";
         break;
       case PCI_CHIP_IVYBRIDGE_S_GT1:
+      case PCI_CHIP_IVYBRIDGE_S_GT2:
         chipset = "Intel(R) Ivybridge Server";
         break;
       case PCI_CHIP_HASWELL_GT1: