MIPS: Rename the "Fill" cache ops to avoid build failure

MIPS define a "Fill" macro as a cache operation in cacheops.h, this
will cause build failure under some special configurations because in
seq_file.c there is a "Fill" label. To avoid this failure we rename the
"Fill" macro to "Fill_I" which has the same coding style as other cache
operations in cacheops.h (we think renaming the "Fill" macro is more
reasonable than renaming the "Fill" label).

Callers of "Fill" macro is also updated.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index 8031fbc..50253ef 100644 (file)
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -48,7 +48,7 @@
  * R4000-specific cacheops
  */
 #define Create_Dirty_Excl_D            (Cache_D | 0x0c)
-#define Fill                           (Cache_I | 0x14)
+#define Fill_I                         (Cache_I | 0x14)
 #define Hit_Writeback_I                        (Cache_I | Hit_Writeback)
 #define Hit_Writeback_D                        (Cache_D | Hit_Writeback)
 

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 36a3113..89b6839 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1049,7 +1049,7 @@ static inline void rm7k_erratum31(void)
                        "cache\t%1, 0x3000(%0)\n\t"
                        ".set pop\n"
                        :
-                       : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
+                       : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill_I));
        }
 }
 

diff --git a/arch/mips/pmcs-msp71xx/msp_setup.c b/arch/mips/pmcs-msp71xx/msp_setup.c
index d1e59ce..e0f20f4 100644 (file)
--- a/arch/mips/pmcs-msp71xx/msp_setup.c
+++ b/arch/mips/pmcs-msp71xx/msp_setup.c
@@ -55,7 +55,7 @@ void msp7120_reset(void)
 
        for (iptr = (void *)((unsigned int)start & ~(L1_CACHE_BYTES - 1));
             iptr < end; iptr += L1_CACHE_BYTES)
-               cache_op(Fill, iptr);
+               cache_op(Fill_I, iptr);
 
        __asm__ __volatile__ (
                "startpoint:                                    \n"