KVM: LAPIC: Set the TDCR settable bits

It is a little different between Intel and AMD, Intel's bit 2
is 0 and AMD is reserved. On bare-metal, Intel will refuse to set
APIC_TDCR once bits except 0, 1, 3 are setting, however, AMD will
accept bits 0, 1, 3 and ignore other bits setting as patch does.
Before the patch, we can get back anything what we set to the
APIC_TDCR, this patch improves it.

Signed-off-by: Wanpeng Li <wanpengli@tencent.com>
Message-Id: <1596165141-28874-2-git-send-email-wanpengli@tencent.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index d5fb2ea..bd16e31 100644 (file)
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -2066,7 +2066,7 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
        case APIC_TDCR: {
                uint32_t old_divisor = apic->divide_count;
 
-               kvm_lapic_set_reg(apic, APIC_TDCR, val);
+               kvm_lapic_set_reg(apic, APIC_TDCR, val & 0xb);
                update_divide_count(apic);
                if (apic->divide_count != old_divisor &&
                                apic->lapic_timer.period) {