arm64: dts: n5x: Add support for Intel's eASIC N5X platform

The Intel eASIC N5X platform shares the same register map as the Agilex
platform, thus, we can re-use the socfpga_agilex.dtsi as the base
DTSI.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 6eecdef..c20eacd 100644 (file)
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -13,6 +13,11 @@ config ARCH_AGILEX
        help
          This enables support for Intel's Agilex SoCFPGA Family.
 
+config ARCH_N5X
+       bool "Intel's eASIC N5X SoCFPGA Family"
+       help
+         This enables support for Intel's eASIC N5X SoCFPGA Family.
+
 config ARCH_SUNXI
        bool "Allwinner sunxi 64-bit SoC Family"
        select ARCH_HAS_RESET_CONTROLLER

diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
index 296ecee..3a05254 100644 (file)
--- a/arch/arm64/boot/dts/intel/Makefile
+++ b/arch/arm64/boot/dts/intel/Makefile
@@ -2,3 +2,4 @@
 dtb-$(CONFIG_ARCH_AGILEX) += socfpga_agilex_socdk.dtb \
                             socfpga_agilex_socdk_nand.dtb
 dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
+dtb-$(CONFIG_ARCH_N5X) += socfpga_n5x_socdk.dtb

diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
new file mode 100644 (file)
index 0000000..5f56e26
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier:     GPL-2.0
+/*
+ * Copyright (C) 2021, Intel Corporation
+ */
+#include "socfpga_agilex.dtsi"
+
+/ {
+       model = "eASIC N5X SoCDK";
+
+       aliases {
+               serial0 = &uart0;
+               ethernet0 = &gmac0;
+               ethernet1 = &gmac1;
+               ethernet2 = &gmac2;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory {
+               device_type = "memory";
+               /* We expect the bootloader to fill in the reg */
+               reg = <0 0 0 0>;
+       };
+
+       soc {
+               clocks {
+                       osc1 {
+                               clock-frequency = <25000000>;
+                       };
+               };
+       };
+};
+
+&clkmgr {
+       compatible = "intel,easic-n5x-clkmgr";
+};
+
+&mmc {
+       status = "okay";
+       cap-sd-highspeed;
+       broken-cd;
+       bus-width = <4>;
+};
+
+&uart0 {
+       status = "okay";
+};
+
+&watchdog0 {
+       status = "okay";
+};