drm/msm/dpu: make dpu_hw_ctl_clear_all_blendstages clear necessary LMs

dpu_hw_ctl_clear_all_blendstages() clears settings for the few first LMs
instead of mixers actually used for the CTL. Change it to clear
necessary data, using provided mixer ids.

Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210704230519.4081467-1-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index f8a74f6..64740dd 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -345,10 +345,12 @@ static void dpu_hw_ctl_clear_all_blendstages(struct dpu_hw_ctl *ctx)
        int i;
 
        for (i = 0; i < ctx->mixer_count; i++) {
-               DPU_REG_WRITE(c, CTL_LAYER(LM_0 + i), 0);
-               DPU_REG_WRITE(c, CTL_LAYER_EXT(LM_0 + i), 0);
-               DPU_REG_WRITE(c, CTL_LAYER_EXT2(LM_0 + i), 0);
-               DPU_REG_WRITE(c, CTL_LAYER_EXT3(LM_0 + i), 0);
+               enum dpu_lm mixer_id = ctx->mixer_hw_caps[i].id;
+
+               DPU_REG_WRITE(c, CTL_LAYER(mixer_id), 0);
+               DPU_REG_WRITE(c, CTL_LAYER_EXT(mixer_id), 0);
+               DPU_REG_WRITE(c, CTL_LAYER_EXT2(mixer_id), 0);
+               DPU_REG_WRITE(c, CTL_LAYER_EXT3(mixer_id), 0);
        }
 
        DPU_REG_WRITE(c, CTL_FETCH_PIPE_ACTIVE, 0);