ret float %t5
}
+define amdgpu_ps float @fmac_sequence_innermost_fmul_multiple_use(float inreg %a, float inreg %b, float inreg %c, float inreg %d, float inreg %e, float inreg %f, float %g) #0 {
+; GCN-LABEL: fmac_sequence_innermost_fmul_multiple_use:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_mac_f32_e64 v0, s2, s3
+; GCN-NEXT: v_fmac_f32_e64 v0, s0, s1
+; GCN-NEXT: v_fma_f32 v1, s5, s4, v0
+; GCN-NEXT: v_fmac_f32_e32 v0, s5, v1
+; GCN-NEXT: ; return to shader part epilog
+ %t0 = fmul fast float %a, %b
+ %t1 = fmul fast float %c, %d
+ %t2 = fadd fast float %t0, %t1
+ %t3 = fmul fast float %e, %f
+ %t4 = fadd fast float %t2, %t3
+ %t5 = fmul fast float %f, %t4
+ %t6 = fadd fast float %t5, %t2
+ %t7 = fadd fast float %t6, %g
+ ret float %t7
+}
+
; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
declare float @llvm.maxnum.f32(float, float) #1