{
struct amdgpu_device *adev = dev_get_drvdata(dev);
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
- int limit_type = to_sensor_dev_attr(attr)->index;
- uint32_t limit = limit_type << 24;
+ enum pp_power_type power_type = to_sensor_dev_attr(attr)->index;
+ uint32_t limit;
uint32_t max_limit = 0;
ssize_t size;
int r;
}
if (is_support_sw_smu(adev)) {
- smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_MAX);
+ smu_get_power_limit(&adev->smu, &limit, PP_PWR_LIMIT_MAX, power_type);
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
} else if (pp_funcs && pp_funcs->get_power_limit) {
pp_funcs->get_power_limit(adev->powerplay.pp_handle,
{
struct amdgpu_device *adev = dev_get_drvdata(dev);
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
- int limit_type = to_sensor_dev_attr(attr)->index;
- uint32_t limit = limit_type << 24;
+ enum pp_power_type power_type = to_sensor_dev_attr(attr)->index;
+ uint32_t limit;
ssize_t size;
int r;
}
if (is_support_sw_smu(adev)) {
- smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_CURRENT);
+ smu_get_power_limit(&adev->smu, &limit, PP_PWR_LIMIT_CURRENT, power_type);
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
} else if (pp_funcs && pp_funcs->get_power_limit) {
pp_funcs->get_power_limit(adev->powerplay.pp_handle,
{
struct amdgpu_device *adev = dev_get_drvdata(dev);
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
- int limit_type = to_sensor_dev_attr(attr)->index;
- uint32_t limit = limit_type << 24;
+ enum pp_power_type power_type = to_sensor_dev_attr(attr)->index;
+ uint32_t limit;
ssize_t size;
int r;
}
if (is_support_sw_smu(adev)) {
- smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_DEFAULT);
+ smu_get_power_limit(&adev->smu, &limit, PP_PWR_LIMIT_DEFAULT, power_type);
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
} else if (pp_funcs && pp_funcs->get_power_limit) {
pp_funcs->get_power_limit(adev->powerplay.pp_handle,
int smu_get_power_limit(struct smu_context *smu,
uint32_t *limit,
- enum smu_ppt_limit_level limit_level)
+ enum pp_power_limit_level pp_limit_level,
+ enum pp_power_type pp_power_type)
{
- uint32_t limit_type = *limit >> 24;
+ enum smu_ppt_limit_level limit_level;
+ uint32_t limit_type;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
return -EOPNOTSUPP;
+ switch(pp_power_type) {
+ case PP_PWR_TYPE_SUSTAINED:
+ limit_type = SMU_DEFAULT_PPT_LIMIT;
+ break;
+ case PP_PWR_TYPE_FAST:
+ limit_type = SMU_FAST_PPT_LIMIT;
+ break;
+ default:
+ return -EOPNOTSUPP;
+ break;
+ }
+
+ switch(pp_limit_level){
+ case PP_PWR_LIMIT_CURRENT:
+ limit_level = SMU_PPT_LIMIT_CURRENT;
+ break;
+ case PP_PWR_LIMIT_DEFAULT:
+ limit_level = SMU_PPT_LIMIT_DEFAULT;
+ break;
+ case PP_PWR_LIMIT_MAX:
+ limit_level = SMU_PPT_LIMIT_MAX;
+ break;
+ case PP_PWR_LIMIT_MIN:
+ default:
+ return -EOPNOTSUPP;
+ break;
+ }
+
mutex_lock(&smu->mutex);
if (limit_type != SMU_DEFAULT_PPT_LIMIT) {