amdgpu/pm: clean up smu_get_power_limit function signature

 add two new powerplay enums (limit_level, type)
 add enums to smu_get_power_limit signature
 remove input bitfield stuffing of output variable limit
 update calls to smu_get_power_limit

* Test
 AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1`
 AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f 11`
 HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON}

 lspci -nn | grep "VGA\|Display" ; \
 echo "=== power1 cap ===" ; cat $HWMON_DIR/power1_cap ;           \
 echo "=== power1 cap max ===" ; cat $HWMON_DIR/power1_cap_max ;   \
 echo "=== power1 cap def ===" ; cat $HWMON_DIR/power1_cap_default

Signed-off-by: Darren Powell <darren.powell@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 7bc7492..6689164 100644 (file)
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -194,6 +194,20 @@ enum pp_df_cstate {
        DF_CSTATE_ALLOW,
 };
 
+enum pp_power_limit_level
+{
+       PP_PWR_LIMIT_MIN = -1,
+       PP_PWR_LIMIT_CURRENT,
+       PP_PWR_LIMIT_DEFAULT,
+       PP_PWR_LIMIT_MAX,
+};
+
+enum pp_power_type
+{
+       PP_PWR_TYPE_SUSTAINED,
+       PP_PWR_TYPE_FAST,
+};
+
 #define PP_GROUP_MASK        0xF0000000
 #define PP_GROUP_SHIFT       28
 

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 2e1286f..c827f0a 100644 (file)
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2907,8 +2907,8 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
 {
        struct amdgpu_device *adev = dev_get_drvdata(dev);
        const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
-       int limit_type = to_sensor_dev_attr(attr)->index;
-       uint32_t limit = limit_type << 24;
+       enum pp_power_type power_type = to_sensor_dev_attr(attr)->index;
+       uint32_t limit;
        uint32_t max_limit = 0;
        ssize_t size;
        int r;
@@ -2925,7 +2925,7 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
        }
 
        if (is_support_sw_smu(adev)) {
-               smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_MAX);
+               smu_get_power_limit(&adev->smu, &limit, PP_PWR_LIMIT_MAX, power_type);
                size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
        } else if (pp_funcs && pp_funcs->get_power_limit) {
                pp_funcs->get_power_limit(adev->powerplay.pp_handle,
@@ -2947,8 +2947,8 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
 {
        struct amdgpu_device *adev = dev_get_drvdata(dev);
        const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
-       int limit_type = to_sensor_dev_attr(attr)->index;
-       uint32_t limit = limit_type << 24;
+       enum pp_power_type power_type = to_sensor_dev_attr(attr)->index;
+       uint32_t limit;
        ssize_t size;
        int r;
 
@@ -2964,7 +2964,7 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
        }
 
        if (is_support_sw_smu(adev)) {
-               smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_CURRENT);
+               smu_get_power_limit(&adev->smu, &limit, PP_PWR_LIMIT_CURRENT, power_type);
                size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
        } else if (pp_funcs && pp_funcs->get_power_limit) {
                pp_funcs->get_power_limit(adev->powerplay.pp_handle,
@@ -2986,8 +2986,8 @@ static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
 {
        struct amdgpu_device *adev = dev_get_drvdata(dev);
        const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
-       int limit_type = to_sensor_dev_attr(attr)->index;
-       uint32_t limit = limit_type << 24;
+       enum pp_power_type power_type = to_sensor_dev_attr(attr)->index;
+       uint32_t limit;
        ssize_t size;
        int r;
 
@@ -3003,7 +3003,7 @@ static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
        }
 
        if (is_support_sw_smu(adev)) {
-               smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_DEFAULT);
+               smu_get_power_limit(&adev->smu, &limit, PP_PWR_LIMIT_DEFAULT, power_type);
                size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
        } else if (pp_funcs && pp_funcs->get_power_limit) {
                pp_funcs->get_power_limit(adev->powerplay.pp_handle,

diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 71adb9e..026d9b6 100644 (file)
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -1264,7 +1264,8 @@ enum smu_cmn2asic_mapping_type {
 #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4)
 int smu_get_power_limit(struct smu_context *smu,
                        uint32_t *limit,
-                       enum smu_ppt_limit_level limit_level);
+                       enum pp_power_limit_level pp_limit_level,
+                       enum pp_power_type pp_power_type);
 
 bool smu_mode1_reset_is_support(struct smu_context *smu);
 bool smu_mode2_reset_is_support(struct smu_context *smu);

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 1b8321d..cfa6808 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -2175,14 +2175,44 @@ static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
 
 int smu_get_power_limit(struct smu_context *smu,
                        uint32_t *limit,
-                       enum smu_ppt_limit_level limit_level)
+                       enum pp_power_limit_level pp_limit_level,
+                       enum pp_power_type pp_power_type)
 {
-       uint32_t limit_type = *limit >> 24;
+       enum smu_ppt_limit_level limit_level;
+       uint32_t limit_type;
        int ret = 0;
 
        if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
                return -EOPNOTSUPP;
 
+       switch(pp_power_type) {
+       case PP_PWR_TYPE_SUSTAINED:
+               limit_type = SMU_DEFAULT_PPT_LIMIT;
+               break;
+       case PP_PWR_TYPE_FAST:
+               limit_type = SMU_FAST_PPT_LIMIT;
+               break;
+       default:
+               return -EOPNOTSUPP;
+               break;
+       }
+
+       switch(pp_limit_level){
+       case PP_PWR_LIMIT_CURRENT:
+               limit_level = SMU_PPT_LIMIT_CURRENT;
+               break;
+       case PP_PWR_LIMIT_DEFAULT:
+               limit_level = SMU_PPT_LIMIT_DEFAULT;
+               break;
+       case PP_PWR_LIMIT_MAX:
+               limit_level = SMU_PPT_LIMIT_MAX;
+               break;
+       case PP_PWR_LIMIT_MIN:
+       default:
+               return -EOPNOTSUPP;
+               break;
+       }
+
        mutex_lock(&smu->mutex);
 
        if (limit_type != SMU_DEFAULT_PPT_LIMIT) {