dts: add riscv include prefix link
authorAndre Przywara <andre.przywara@arm.com>
Mon, 20 Mar 2023 00:52:46 +0000 (00:52 +0000)
committerJernej Skrabec <jernej.skrabec@gmail.com>
Mon, 27 Mar 2023 20:45:22 +0000 (22:45 +0200)
The Allwinner D1/D1s SoCs (with a RISC-V core) use an (almost?) identical
die as their R528/T113-s siblings with ARM Cortex-A7 cores.

To allow sharing the basic SoC .dtsi files across those two
architectures as well, introduce a symlink to the RISC-V DT directory.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20230320005249.13403-2-andre.przywara@arm.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
scripts/dtc/include-prefixes/riscv [new symlink]

diff --git a/scripts/dtc/include-prefixes/riscv b/scripts/dtc/include-prefixes/riscv
new file mode 120000 (symlink)
index 0000000..2025094
--- /dev/null
@@ -0,0 +1 @@
+../../../arch/riscv/boot/dts
\ No newline at end of file