VPP: haswell: fix video post-processing setup.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

diff --git a/src/i965_post_processing.c b/src/i965_post_processing.c
index 2f16a20..459d2c5 100755 (executable)
--- a/src/i965_post_processing.c
+++ b/src/i965_post_processing.c
@@ -1145,6 +1145,7 @@ gen7_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_cont
                           int width, int height, int pitch, int format, 
                           int index, int is_target)
 {
+    struct i965_driver_data * const i965 = i965_driver_data(ctx);  
     struct gen7_surface_state *ss;
     dri_bo *ss_bo;
     unsigned int tiling;
@@ -1165,6 +1166,8 @@ gen7_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_cont
     ss->ss2.height = height - 1;
     ss->ss3.pitch = pitch - 1;
     gen7_pp_set_surface_tiling(ss, tiling);
+    if (IS_HASWELL(i965->intel.device_id))
+        gen7_render_set_surface_scs(ss);
     dri_bo_emit_reloc(ss_bo,
                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
                       surf_bo_offset,

diff --git a/src/i965_render.c b/src/i965_render.c
index 9b277af..4a72b56 100644 (file)
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -729,7 +729,7 @@ gen7_render_set_surface_tiling(struct gen7_surface_state *ss, uint32_t tiling)
 }
 
 /* Set "Shader Channel Select" */
-static void
+void
 gen7_render_set_surface_scs(struct gen7_surface_state *ss)
 {
     ss->ss7.shader_chanel_select_r = HSW_SCS_RED;

diff --git a/src/i965_render.h b/src/i965_render.h
index 96a1512..c2fc2bf 100644 (file)
--- a/src/i965_render.h
+++ b/src/i965_render.h
@@ -98,4 +98,9 @@ intel_render_put_subpicture(
     const VARectangle *dst_rect
 );
 
+struct gen7_surface_state;
+
+void
+gen7_render_set_surface_scs(struct gen7_surface_state *ss);
+
 #endif /* _I965_RENDER_H_ */