}
if (bo->ptr)
- os_munmap(bo->ptr, bo->size);
+ os_munmap(bo->ptr, bo->base.size);
/* Close object. */
args.handle = bo->handle;
}
args.handle = bo->handle;
args.offset = 0;
- args.size = (uint64_t)bo->size;
+ args.size = (uint64_t)bo->base.size;
if (drmCommandWriteRead(bo->rws->fd,
DRM_RADEON_GEM_MMAP,
&args,
bo->mgr = mgr;
bo->rws = mgr->rws;
bo->handle = args.handle;
- bo->size = size;
pipe_mutex_init(bo->map_mutex);
return &bo->base;
goto fail;
}
bo->handle = open_arg.handle;
- bo->size = open_arg.size;
bo->name = whandle->handle;
/* Initialize it. */
pipe_reference_init(&bo->base.reference, 1);
bo->base.alignment = 0;
bo->base.usage = PB_USAGE_GPU_WRITE | PB_USAGE_GPU_READ;
- bo->base.size = bo->size;
+ bo->base.size = open_arg.size;
bo->base.vtbl = &radeon_bo_vtbl;
bo->mgr = mgr;
bo->rws = mgr->rws;
unsigned index = radeon_add_reloc(cs->csc, bo, rd, wd, &added_domains);
if (added_domains & RADEON_DOMAIN_GTT)
- cs->csc->used_gart += bo->size;
+ cs->csc->used_gart += bo->base.size;
if (added_domains & RADEON_DOMAIN_VRAM)
- cs->csc->used_vram += bo->size;
+ cs->csc->used_vram += bo->base.size;
return index;
}