Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
*/
device->has_clear_state = device->rad_info.chip_class >= CIK;
+ device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
+
radv_physical_device_init_mem_types(device);
result = radv_init_wsi(device);
bool has_rbplus; /* if RB+ register exist */
bool rbplus_allowed; /* if RB+ is allowed */
bool has_clear_state;
+ bool cpdma_prefetch_writes_memory;
/* This is the drivers on-disk cache used as a fallback as opposed to
* the pipeline cache defined by apps.
slab->size = 256 * 1024;
slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
- RADEON_DOMAIN_VRAM, RADEON_FLAG_NO_INTERPROCESS_SHARING);
+ RADEON_DOMAIN_VRAM,
+ RADEON_FLAG_NO_INTERPROCESS_SHARING |
+ device->physical_device->cpdma_prefetch_writes_memory ?
+ 0 : RADEON_FLAG_READ_ONLY);
slab->ptr = (char*)device->ws->buffer_map(slab->bo);
list_inithead(&slab->shaders);