ARM: dts: exynos: change vpll clock to 600MHz

This change enhances MALI inference(on-device deep leanring) performance.

Change-Id: I2a9341589873a049bd91ee6771c96d831768df3c
Signed-off-by: Inki Dae <inki.dae@samsung.com>

diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 6ebd184ce5e3377bf262a1ddbcfe041e019b32e1..652274eaf7b3532a2a96442165c436086fa273e5 100644 (file)
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -422,6 +422,8 @@
 
 &mali {
        mali-supply = <&buck4_reg>;
+       assigned-clocks = <&clock CLK_FOUT_VPLL>;
+       assigned-clock-rates = <600000000>;
        status = "okay";
 };