drm/exynos/hdmi: stop programming registers with default values

There is no point in rewriting default values, as the IP is reset anyway.

Change-Id: I9c0856d48be83a36ed4a8741e86715353acbf2d0
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>

diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c
index ea70e0d33181c48b7fbe1228faeeec612645ec62..1755ed3b01dd0e318127ea31d4d2b0c9c58267df 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -1644,7 +1644,6 @@ static void hdmi_v13_mode_apply(struct hdmi_context *hdata)
                hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
                                m->vtotal - m->vdisplay);
                hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay);
-               hdmi_reg_writev(hdata, HDMI_TG_VACT_ST2_L, 2, 0x248);
        }
 
        /* Timing generator registers */
@@ -1652,13 +1651,6 @@ static void hdmi_v13_mode_apply(struct hdmi_context *hdata)
        hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2, m->htotal - m->hdisplay);
        hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay);
        hdmi_reg_writev(hdata, HDMI_TG_V_FSZ_L, 2, m->vtotal);
-       hdmi_reg_writev(hdata, HDMI_TG_VSYNC_L, 2, 0x1);
-       hdmi_reg_writev(hdata, HDMI_TG_VSYNC2_L, 2, 0x233);
-       hdmi_reg_writev(hdata, HDMI_TG_FIELD_CHG_L, 2, 0x233);
-       hdmi_reg_writev(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, 2, 0x1);
-       hdmi_reg_writev(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, 2, 0x233);
-       hdmi_reg_writev(hdata, HDMI_TG_FIELD_TOP_HDMI_L, 2, 0x1);
-       hdmi_reg_writev(hdata, HDMI_TG_FIELD_BOT_HDMI_L, 2, 0x233);
 }
 
 static void hdmi_v14_mode_apply(struct hdmi_context *hdata)
@@ -1733,12 +1725,6 @@ static void hdmi_v14_mode_apply(struct hdmi_context *hdata)
                hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
                                m->vtotal - m->vdisplay);
                hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay);
-               hdmi_reg_writev(hdata, HDMI_TG_VACT_ST2_L, 2, 0x248);
-               hdmi_reg_writev(hdata, HDMI_TG_VACT_ST3_L, 2, 0x47b);
-               hdmi_reg_writev(hdata, HDMI_TG_VACT_ST4_L, 2, 0x6ae);
-               hdmi_reg_writev(hdata, HDMI_TG_VSYNC2_L, 2, 0x233);
-               hdmi_reg_writev(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, 2, 0x233);
-               hdmi_reg_writev(hdata, HDMI_TG_FIELD_BOT_HDMI_L, 2, 0x233);
        }
 
        /* Following values & calculations are same irrespective of mode type */
@@ -1770,12 +1756,6 @@ static void hdmi_v14_mode_apply(struct hdmi_context *hdata)
        hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2, m->htotal - m->hdisplay);
        hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay);
        hdmi_reg_writev(hdata, HDMI_TG_V_FSZ_L, 2, m->vtotal);
-       hdmi_reg_writev(hdata, HDMI_TG_VSYNC_L, 2, 0x1);
-       hdmi_reg_writev(hdata, HDMI_TG_FIELD_CHG_L, 2, 0x233);
-       hdmi_reg_writev(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, 2, 0x1);
-       hdmi_reg_writev(hdata, HDMI_TG_FIELD_TOP_HDMI_L, 2, 0x1);
-       hdmi_reg_writev(hdata, HDMI_TG_3D, 1, 0x0);
-
        if (hdata->drv_data == &exynos5430_hdmi_driver_data)
                hdmi_reg_writeb(hdata, HDMI_TG_DECON_EN, 1);
 }