bool isCCKrate = false;
u8 rf_rx_num = 0;
u8 LNA_idx, VGA_idx;
- struct PHY_STATUS_RPT_8192CD_T *pPhyStaRpt = (struct PHY_STATUS_RPT_8192CD_T *)pPhyStatus;
+ struct phy_status_rpt_8192cd_t *pPhyStaRpt = (struct phy_status_rpt_8192cd_t *)pPhyStatus;
isCCKrate = pPktinfo->data_rate <= DESC_RATE11M;
pPhyInfo->rx_mimo_signal_quality[ODM_RF_PATH_A] = -1;
/* structure and define */
/* */
-struct PHY_RX_AGC_INFO_T {
+struct phy_rx_agc_info_t {
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u8 gain:7, trsw:1;
#else
#endif
};
-struct PHY_STATUS_RPT_8192CD_T {
- struct PHY_RX_AGC_INFO_T path_agc[2];
+struct phy_status_rpt_8192cd_t {
+ struct phy_rx_agc_info_t path_agc[2];
u8 ch_corr[2];
u8 cck_sig_qual_ofdm_pwdb_all;
u8 cck_agc_rpt_ofdm_cfosho_a;
};
-struct PHY_STATUS_RPT_8812_T {
+struct phy_status_rpt_8812_t {
/* 2012.05.24 LukeLee: This structure should take big/little endian in consideration later..... */
/* DWORD 0 */