ARM: dts: meson: add the SAR ADC
authorMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Thu, 15 Jun 2017 21:33:47 +0000 (23:33 +0200)
committerKevin Hilman <khilman@baylibre.com>
Fri, 16 Jun 2017 19:07:10 +0000 (12:07 -0700)
This adds the SAR ADC to meson.dtsi and configures the clocks on Meson8
and Meson8b to allow boards to use it. Some boards use it to connect a
button to it.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
arch/arm/boot/dts/meson.dtsi
arch/arm/boot/dts/meson8.dtsi
arch/arm/boot/dts/meson8b.dtsi

index d287f60..46706d7 100644 (file)
                                status = "disabled";
                        };
 
+                       saradc: adc@8680 {
+                               compatible = "amlogic,meson-saradc";
+                               reg = <0x8680 0x34>;
+                               #io-channel-cells = <1>;
+                               interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
+                               status = "disabled";
+                       };
+
                        uart_C: serial@8700 {
                                compatible = "amlogic,meson-uart";
                                reg = <0x8700 0x18>;
index bb3608b..6687b1b 100644 (file)
        arm,filter-ranges = <0x100000 0xc0000000>;
 };
 
+&saradc {
+       compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
+       clocks = <&clkc CLKID_XTAL>,
+               <&clkc CLKID_SAR_ADC>,
+               <&clkc CLKID_SANA>;
+       clock-names = "clkin", "core", "sana";
+};
+
 &spifc {
        clocks = <&clkc CLKID_CLK81>;
 };
index d9f116a..1c09090 100644 (file)
        arm,filter-ranges = <0x100000 0xc0000000>;
 };
 
+&saradc {
+       compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
+       clocks = <&clkc CLKID_XTAL>,
+               <&clkc CLKID_SAR_ADC>,
+               <&clkc CLKID_SANA>;
+       clock-names = "clkin", "core", "sana";
+};
+
 &uart_AO {
        clocks = <&clkc CLKID_CLK81>;
 };