drm/msm/dsi: Use division result from div_u64_rem in 7nm and 14nm PLL

div_u64_rem provides the result of the division and additionally the
remainder; don't use this function to solely calculate the remainder
while calculating the division again with div_u64.

A similar improvement was applied earlier to the 10nm pll in
5c191fef4ce2 ("drm/msm/dsi_pll_10nm: Fix dividing the same numbers
twice").

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-By: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20211011201642.167700-1-marijn.suijten@somainline.org
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index 5b4e991..c62d903 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -213,9 +213,7 @@ static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll, struct dsi_pll_conf
        DBG("vco_clk_rate=%lld ref_clk_rate=%lld", vco_clk_rate, fref);
 
        dec_start_multiple = div_u64(vco_clk_rate * multiplier, fref);
-       div_u64_rem(dec_start_multiple, multiplier, &div_frac_start);
-
-       dec_start = div_u64(dec_start_multiple, multiplier);
+       dec_start = div_u64_rem(dec_start_multiple, multiplier, &div_frac_start);
 
        pconf->dec_start = (u32)dec_start;
        pconf->div_frac_start = div_frac_start;

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index cb297b0..079613d 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -114,9 +114,7 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config
 
        multiplier = 1 << FRAC_BITS;
        dec_multiple = div_u64(pll_freq * multiplier, divider);
-       div_u64_rem(dec_multiple, multiplier, &frac);
-
-       dec = div_u64(dec_multiple, multiplier);
+       dec = div_u64_rem(dec_multiple, multiplier, &frac);
 
        if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1))
                config->pll_clock_inverters = 0x28;