ARM: dts: imx6ul: add TQ-Systems MBa6ULxL device trees

Add device trees for the MBa6ULx mainboard with TQMa6ULxL SoMs.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index c76742c..e991232 100644 (file)
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -692,6 +692,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
        imx6ul-liteboard.dtb \
        imx6ul-tqma6ul1-mba6ulx.dtb \
        imx6ul-tqma6ul2-mba6ulx.dtb \
+       imx6ul-tqma6ul2l-mba6ulx.dtb \
        imx6ul-opos6uldev.dtb \
        imx6ul-pico-dwarf.dtb \
        imx6ul-pico-hobbit.dtb \

diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts b/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts
new file mode 100644 (file)
index 0000000..9d9b6b7
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+/dts-v1/;
+
+#include "imx6ul-tqma6ul2l.dtsi"
+#include "mba6ulx.dtsi"
+
+/ {
+       model = "TQ Systems TQMa6UL2L SoM on MBa6ULx board";
+       compatible = "tq,imx6ul-tqma6ul2l-mba6ulx", "tq,imx6ul-tqma6ul2l", "fsl,imx6ul";
+};

diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi
new file mode 100644 (file)
index 0000000..caf2c5d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ-Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+#include "imx6ul.dtsi"
+#include "imx6ul-tqma6ul-common.dtsi"
+#include "imx6ul-tqma6ulxl-common.dtsi"
+
+/ {
+       model = "TQ-Systems TQMa6UL2L SoM";
+       compatible = "tq,imx6ul-tqma6ul2l", "fsl,imx6ul";
+};
+
+&usdhc2 {
+       fsl,tuning-step= <6>;
+};
+
+&iomuxc {
+       pinctrl_usdhc2: usdhc2grp {
+               fsl,pins = <
+                       MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x00017051
+                       MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x00017051
+                       MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x00017051
+                       MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x00017051
+                       MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x00017051
+                       MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x00017051
+                       MX6UL_PAD_NAND_DATA04__USDHC2_DATA4     0x00017051
+                       MX6UL_PAD_NAND_DATA05__USDHC2_DATA5     0x00017051
+                       MX6UL_PAD_NAND_DATA06__USDHC2_DATA6     0x00017051
+                       MX6UL_PAD_NAND_DATA07__USDHC2_DATA7     0x00017051
+                       /* rst */
+                       MX6UL_PAD_NAND_ALE__GPIO4_IO10          0x0001b051
+               >;
+       };
+
+       pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+               fsl,pins = <
+                       MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x000170e1
+                       MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x000170f1
+                       MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x000170f1
+                       MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x000170f1
+                       MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x000170f1
+                       MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x000170f1
+                       MX6UL_PAD_NAND_DATA04__USDHC2_DATA4     0x000170f1
+                       MX6UL_PAD_NAND_DATA05__USDHC2_DATA5     0x000170f1
+                       MX6UL_PAD_NAND_DATA06__USDHC2_DATA6     0x000170f1
+                       MX6UL_PAD_NAND_DATA07__USDHC2_DATA7     0x000170f1
+                       /* rst */
+                       MX6UL_PAD_NAND_ALE__GPIO4_IO10          0x0001b051
+               >;
+       };
+
+       pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+               fsl,pins = <
+                       MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x000170f9
+                       MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x000170f1
+                       MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x000170f1
+                       MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x000170f1
+                       MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x000170f1
+                       MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x000170f1
+                       MX6UL_PAD_NAND_DATA04__USDHC2_DATA4     0x000170f1
+                       MX6UL_PAD_NAND_DATA05__USDHC2_DATA5     0x000170f1
+                       MX6UL_PAD_NAND_DATA06__USDHC2_DATA6     0x000170f1
+                       MX6UL_PAD_NAND_DATA07__USDHC2_DATA7     0x000170f1
+                       /* rst */
+                       MX6UL_PAD_NAND_ALE__GPIO4_IO10          0x0001b051
+               >;
+       };
+};

diff --git a/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi
new file mode 100644 (file)
index 0000000..ba84a4f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2018-2022 TQ-Systems GmbH
+ * Author: Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+/*
+ * Common for
+ * - TQMa6ULxL
+ * - TQMa6ULLxL
+ */
+
+/ {
+       reg_vin: reg-vin {
+               compatible = "regulator-fixed";
+               regulator-name = "VIN";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-always-on;
+       };
+};
+
+&m24c64_50 {
+       vcc-supply = <&reg_vin>;
+};
+
+&m24c02_52 {
+       vcc-supply = <&reg_vin>;
+};
+
+/* eMMC */
+&usdhc2 {
+       vmmc-supply = <&reg_vin>;
+       vqmmc-supply = <&reg_vldo4>;
+};
+
+&iomuxc {
+       pinctrl_qspi: qspigrp {
+               fsl,pins = <
+                       MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK      0x70a9
+                       MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a9
+                       MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01   0x70a9
+                       MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02   0x70a9
+                       MX6UL_PAD_NAND_CLE__QSPI_A_DATA03     0x70a9
+                       MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B      0x70a1
+               >;
+       };
+};