net: socionext: Add dummy PHY register read in phy_write()

There is a compatibility issue between RTL8211E implemented
in Developerbox and netsec ethernet controller IP.

Our MDIO controller stops MDC clock right after the write
access, but RTL8211E expects MDC clock must be kept toggling
for several clock cycle with MDIO high before entering
the IDLE state. Without keeping clock after write access,
write access is not correctly handled and register is not
updated.

To meet this requirement, netsec driver needs to issue dummy
read(e.g. read PHYID1(offset 0x2) register) right after write
access, to keep MDC clock.

We think this compatibility issue is a problem specific to
our MDIO controller and RTL8211E.

Fixes: 533dd11a12f6 ("net: socionext: Add Synquacer NetSec driver")
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Yoshitoyo Osaki <osaki.yoshitoyo@socionext.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/socionext/netsec.c b/drivers/net/ethernet/socionext/netsec.c
index bd9660ab0701ffc36d6c089e6568eb346b17d880..dbf71e1fa701df30d15a0232178a415066afec28 100644 (file)
--- a/drivers/net/ethernet/socionext/netsec.c
+++ b/drivers/net/ethernet/socionext/netsec.c
@@ -432,9 +432,12 @@ static int netsec_mac_update_to_phy_state(struct netsec_priv *priv)
        return 0;
 }
 
+static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr);
+
 static int netsec_phy_write(struct mii_bus *bus,
                            int phy_addr, int reg, u16 val)
 {
+       int status;
        struct netsec_priv *priv = bus->priv;
 
        if (netsec_mac_write(priv, GMAC_REG_GDR, val))
@@ -447,8 +450,19 @@ static int netsec_phy_write(struct mii_bus *bus,
                              GMAC_REG_SHIFT_CR_GAR)))
                return -ETIMEDOUT;
 
-       return netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
-                                         NETSEC_GMAC_GAR_REG_GB);
+       status = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
+                                           NETSEC_GMAC_GAR_REG_GB);
+
+       /* Developerbox implements RTL8211E PHY and there is
+        * a compatibility problem with F_GMAC4.
+        * RTL8211E expects MDC clock must be kept toggling for several
+        * clock cycle with MDIO high before entering the IDLE state.
+        * To meet this requirement, netsec driver needs to issue dummy
+        * read(e.g. read PHYID1(offset 0x2) register) right after write.
+        */
+       netsec_phy_read(bus, phy_addr, MII_PHYSID1);
+
+       return status;
 }
 
 static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr)