Support for systems based on the DC21285 companion chip
("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
-config ARCH_IOP32X
- bool "IOP32x-based"
- select CPU_XSCALE
- select GPIO_IOP
- select GPIOLIB
- select FORCE_PCI
- select PLAT_IOP
- help
- Support for Intel's 80219 and IOP32X (XScale) family of
- processors.
-
config ARCH_IXP4XX
bool "IXP4xx-based"
select ARCH_SUPPORTS_BIG_ENDIAN
config ARCH_ACORN
bool
-config PLAT_IOP
- bool
-
config PLAT_ORION
bool
select CLKSRC_MMIO
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_IOP32X=y
CONFIG_MACH_GLANTANK=y
CONFIG_ARCH_IQ80321=y
# SPDX-License-Identifier: GPL-2.0
-if ARCH_IOP32X
-
-menu "IOP32x Implementation Options"
+menuconfig ARCH_IOP32X
+ bool "IOP32x-based platforms"
+ depends on ARCH_MULTI_V5
+ select CPU_XSCALE
+ select GPIO_IOP
+ select GPIOLIB
+ select FORCE_PCI
+ help
+ Support for Intel's 80219 and IOP32X (XScale) family of
+ processors.
-comment "IOP32x Platform Types"
+if ARCH_IOP32X
config MACH_EP80219
bool
board. Say also Y here if you have a SS4000e Baxter Creek NAS
appliance."
-endmenu
-
endif
MACHINE_START(EM7210, "Lanner EM7210")
.atag_offset = 0x100,
+ .nr_irqs = IOP32X_NR_IRQS,
.map_io = em7210_map_io,
.init_irq = iop32x_init_irq,
.init_time = em7210_timer_init,
MACHINE_START(GLANTANK, "GLAN Tank")
/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
.atag_offset = 0x100,
+ .nr_irqs = IOP32X_NR_IRQS,
.map_io = glantank_map_io,
.init_irq = iop32x_init_irq,
.init_time = glantank_timer_init,
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-iop32x/include/mach/irqs.h
- *
- * Author: Rory Bolt <rorybolt@pacbell.net>
- * Copyright: (C) 2002 Rory Bolt
- */
-
-#ifndef __IRQS_H
-#define __IRQS_H
-
-#define NR_IRQS 33
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * arch/arm/mach-iop32x/include/mach/uncompress.h
- */
-
-#include <asm/types.h>
-#include <asm/mach-types.h>
-#include <linux/serial_reg.h>
-
-#define uart_base ((volatile u8 *)0xfe800000)
-
-#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
-
-static inline void putc(char c)
-{
- while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
- barrier();
- uart_base[UART_TX] = c;
-}
-
-static inline void flush(void)
-{
-}
-
-#define arch_decomp_setup() do { } while (0)
MACHINE_START(EP80219, "Intel EP80219")
/* Maintainer: Intel Corp. */
.atag_offset = 0x100,
+ .nr_irqs = IOP32X_NR_IRQS,
.map_io = iq31244_map_io,
.init_irq = iop32x_init_irq,
.init_time = iq31244_timer_init,
MACHINE_START(IQ80321, "Intel IQ80321")
/* Maintainer: Intel Corp. */
.atag_offset = 0x100,
+ .nr_irqs = IOP32X_NR_IRQS,
.map_io = iq80321_map_io,
.init_irq = iop32x_init_irq,
.init_time = iq80321_timer_init,
#define IRQ_IOP32X_XINT3 IOP_IRQ(30)
#define IRQ_IOP32X_HPI IOP_IRQ(31)
+#define IOP32X_NR_IRQS (IRQ_IOP32X_HPI + 1)
+
#endif
MACHINE_START(N2100, "Thecus N2100")
/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
.atag_offset = 0x100,
+ .nr_irqs = IOP32X_NR_IRQS,
.map_io = n2100_map_io,
.init_irq = iop32x_init_irq,
.init_time = n2100_timer_init,