clk: imxrt: Use dts for anatop base address
authorJesse Taube <mr.bossman075@gmail.com>
Thu, 17 Mar 2022 18:33:18 +0000 (14:33 -0400)
committerStefano Babic <sbabic@denx.de>
Tue, 12 Apr 2022 19:08:23 +0000 (21:08 +0200)
In Linux IMX and IMXRT use the device tree to hold the anatop address.
The anatop is used in clock drivers as it controls the internal PLLs
This will move the macro from asm/arch-imxrt to the device tree.
This presumably should also be done with the other IMX boards as well.

Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
arch/arm/dts/imxrt1020-evk-u-boot.dtsi
arch/arm/dts/imxrt1020.dtsi
arch/arm/dts/imxrt1050-evk-u-boot.dtsi
arch/arm/dts/imxrt1050.dtsi
arch/arm/include/asm/arch-imxrt/imx-regs.h
drivers/clk/imx/clk-imxrt1020.c
drivers/clk/imx/clk-imxrt1050.c

index 121665a..9e1b074 100644 (file)
        u-boot,dm-spl;
 };
 
+&anatop {
+       u-boot,dm-spl;
+};
+
 &clks {
        u-boot,dm-spl;
 };
index 5ba314f..13511eb 100644 (file)
                        fsl,mux_mask = <0x7>;
                };
 
+               anatop: anatop@400d8000 {
+                       compatible = "fsl,imxrt-anatop";
+                       reg = <0x400d8000 0x4000>;
+               };
+
                clks: ccm@400fc000 {
                        compatible = "fsl,imxrt1020-ccm";
                        reg = <0x400fc000 0x4000>;
index 3168c2d..617cece 100644 (file)
        u-boot,dm-spl;
 };
 
+&anatop {
+       u-boot,dm-spl;
+};
+
 &clks {
        u-boot,dm-spl;
 };
index 6560a38..09f4712 100644 (file)
                        fsl,mux_mask = <0x7>;
                };
 
+               anatop: anatop@400d8000 {
+                       compatible = "fsl,imxrt-anatop";
+                       reg = <0x400d8000 0x4000>;
+               };
+
                clks: ccm@400fc000 {
                        compatible = "fsl,imxrt1050-ccm";
                        reg = <0x400fc000 0x4000>;
index d01e6ca..ad739ca 100644 (file)
@@ -15,8 +15,6 @@
 #define GPIO4_BASE_ADDR                0x401C4000
 #define GPIO5_BASE_ADDR                0x400C0000
 
-#define ANATOP_BASE_ADDR       0x400d8000
-
 #define MXS_LCDIF_BASE         0x402b8000
 
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
index 3f8b4df..dc91ac5 100644 (file)
@@ -36,7 +36,7 @@ static int imxrt1020_clk_probe(struct udevice *dev)
        void *base;
 
        /* Anatop clocks */
-       base = (void *)ANATOP_BASE_ADDR;
+       base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(), "fsl,imxrt-anatop"));
 
        clk_dm(IMXRT1020_CLK_PLL2_SYS,
               imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "osc",
index 5cb5e3b..d40635d 100644 (file)
@@ -34,7 +34,7 @@ static int imxrt1050_clk_probe(struct udevice *dev)
        void *base;
 
        /* Anatop clocks */
-       base = (void *)ANATOP_BASE_ADDR;
+       base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(), "fsl,imxrt-anatop"));
 
        clk_dm(IMXRT1050_CLK_PLL1_REF_SEL,
               imx_clk_mux("pll1_arm_ref_sel", base + 0x0, 14, 2,