/* disable I2C access to internal EDID ram from HDMI DDC ports */
rep_write_and_or(sd, 0x77, 0xf3, 0x00);
- hdmi_write(sd, 0x69, 0xa3); /* HPA manual */
- /* HPA disable on port A and B */
- io_write_and_or(sd, 0x20, 0xcf, 0x00);
+ if (pdata->hpa_auto) {
+ /* HPA auto, HPA 0.5s after Edid set and Cable detect */
+ hdmi_write(sd, 0x69, 0x5c);
+ } else {
+ /* HPA manual */
+ hdmi_write(sd, 0x69, 0xa3);
+ /* HPA disable on port A and B */
+ io_write_and_or(sd, 0x20, 0xcf, 0x00);
+ }
/* LLC */
io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase);
unsigned sdp_free_run_cbar_en:1;
unsigned sdp_free_run_force:1;
+ /* HPA manual (0) or auto (1), affects HDMI register 0x69 */
+ unsigned hpa_auto:1;
+
struct adv7842_sdp_csc_coeff sdp_csc_coeff;
struct adv7842_sdp_io_sync_adjustment sdp_io_sync_625;