[X86] Mark the ADCX and ADOX instruction as commutable.

llvm-svn: 341752

diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td
index 4aaaac551d923811dfbe8fc9c287bb9e325183d5..8d0d98f5488ac1e22681b4460bf2a6e0e81d0ef0 100644 (file)
--- a/llvm/lib/Target/X86/X86InstrArithmetic.td
+++ b/llvm/lib/Target/X86/X86InstrArithmetic.td
@@ -1309,7 +1309,7 @@ let Predicates = [HasBMI2] in {
 //
 let Predicates = [HasADX], Defs = [EFLAGS], Uses = [EFLAGS],
     Constraints = "$src1 = $dst", AddedComplexity = 10 in {
-  let SchedRW = [WriteADC] in {
+  let SchedRW = [WriteADC], isCommutable = 1 in {
   def ADCX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst),
                    (ins GR32:$src1, GR32:$src2),
                    "adcx{l}\t{$src2, $dst|$dst, $src2}",

diff --git a/llvm/test/CodeGen/X86/adx-commute.mir b/llvm/test/CodeGen/X86/adx-commute.mir
index 22fd44dc3c30916ed807dda5c5f092b0d9e98078..11fb1e641849d9305a539ff12205b437bf95e973 100644 (file)
--- a/llvm/test/CodeGen/X86/adx-commute.mir
+++ b/llvm/test/CodeGen/X86/adx-commute.mir
@@ -81,8 +81,7 @@ body:             |
     ; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: [[COPY3:%[0-9]+]]:gr32 = COPY $edi
     ; CHECK: dead [[COPY3]].sub_8bit:gr32 = ADD8ri [[COPY3]].sub_8bit, -1, implicit-def $eflags
-    ; CHECK: [[COPY4:%[0-9]+]]:gr32 = COPY [[COPY2]]
-    ; CHECK: [[ADCX32rr:%[0-9]+]]:gr32 = ADCX32rr [[ADCX32rr]], [[COPY1]], implicit-def dead $eflags, implicit killed $eflags
+    ; CHECK: [[ADCX32rr:%[0-9]+]]:gr32 = ADCX32rr [[ADCX32rr]], [[COPY2]], implicit-def dead $eflags, implicit killed $eflags
     ; CHECK: [[IMUL32rr:%[0-9]+]]:gr32 = IMUL32rr [[IMUL32rr]], [[COPY2]], implicit-def dead $eflags
     ; CHECK: MOV32mr [[COPY]], 1, $noreg, 0, $noreg, [[IMUL32rr]] :: (store 4 into %ir.res)
     ; CHECK: RET 0
@@ -127,8 +126,7 @@ body:             |
     ; CHECK: [[COPY2:%[0-9]+]]:gr64 = COPY $rsi
     ; CHECK: [[COPY3:%[0-9]+]]:gr32 = COPY $edi
     ; CHECK: dead [[COPY3]].sub_8bit:gr32 = ADD8ri [[COPY3]].sub_8bit, -1, implicit-def $eflags
-    ; CHECK: [[COPY4:%[0-9]+]]:gr64 = COPY [[COPY2]]
-    ; CHECK: [[ADCX64rr:%[0-9]+]]:gr64 = ADCX64rr [[ADCX64rr]], [[COPY1]], implicit-def dead $eflags, implicit killed $eflags
+    ; CHECK: [[ADCX64rr:%[0-9]+]]:gr64 = ADCX64rr [[ADCX64rr]], [[COPY2]], implicit-def dead $eflags, implicit killed $eflags
     ; CHECK: [[IMUL64rr:%[0-9]+]]:gr64 = IMUL64rr [[IMUL64rr]], [[COPY2]], implicit-def dead $eflags
     ; CHECK: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, [[IMUL64rr]] :: (store 8 into %ir.res)
     ; CHECK: RET 0
@@ -173,8 +171,7 @@ body:             |
     ; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: [[COPY3:%[0-9]+]]:gr32 = COPY $edi
     ; CHECK: dead [[COPY3]].sub_8bit:gr32 = ADD8ri [[COPY3]].sub_8bit, 127, implicit-def $eflags
-    ; CHECK: [[COPY4:%[0-9]+]]:gr32 = COPY [[COPY2]]
-    ; CHECK: [[ADOX32rr:%[0-9]+]]:gr32 = ADOX32rr [[ADOX32rr]], [[COPY1]], implicit-def dead $eflags, implicit killed $eflags
+    ; CHECK: [[ADOX32rr:%[0-9]+]]:gr32 = ADOX32rr [[ADOX32rr]], [[COPY2]], implicit-def dead $eflags, implicit killed $eflags
     ; CHECK: [[IMUL32rr:%[0-9]+]]:gr32 = IMUL32rr [[IMUL32rr]], [[COPY2]], implicit-def dead $eflags
     ; CHECK: MOV32mr [[COPY]], 1, $noreg, 0, $noreg, [[IMUL32rr]] :: (store 4 into %ir.res)
     ; CHECK: RET 0
@@ -219,8 +216,7 @@ body:             |
     ; CHECK: [[COPY2:%[0-9]+]]:gr64 = COPY $rsi
     ; CHECK: [[COPY3:%[0-9]+]]:gr32 = COPY $edi
     ; CHECK: dead [[COPY3]].sub_8bit:gr32 = ADD8ri [[COPY3]].sub_8bit, 127, implicit-def $eflags
-    ; CHECK: [[COPY4:%[0-9]+]]:gr64 = COPY [[COPY2]]
-    ; CHECK: [[ADOX64rr:%[0-9]+]]:gr64 = ADOX64rr [[ADOX64rr]], [[COPY1]], implicit-def dead $eflags, implicit killed $eflags
+    ; CHECK: [[ADOX64rr:%[0-9]+]]:gr64 = ADOX64rr [[ADOX64rr]], [[COPY2]], implicit-def dead $eflags, implicit killed $eflags
     ; CHECK: [[IMUL64rr:%[0-9]+]]:gr64 = IMUL64rr [[IMUL64rr]], [[COPY2]], implicit-def dead $eflags
     ; CHECK: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, [[IMUL64rr]] :: (store 8 into %ir.res)
     ; CHECK: RET 0

diff --git a/llvm/test/CodeGen/X86/pr32282.ll b/llvm/test/CodeGen/X86/pr32282.ll
index ed1ec07c851e766943ec776b3f36b3d124477b9b..f5e4a0174ad267d9b773e156c7fff60da73f468c 100644 (file)
--- a/llvm/test/CodeGen/X86/pr32282.ll
+++ b/llvm/test/CodeGen/X86/pr32282.ll
@@ -25,8 +25,8 @@ define void @foo() {
 ; X86-NEXT:    andl $-2, %eax
 ; X86-NEXT:    xorl %edx, %edx
 ; X86-NEXT:    addl $7, %eax
-; X86-NEXT:    adcxl %edx, %ecx
-; X86-NEXT:    pushl %ecx
+; X86-NEXT:    adcxl %ecx, %edx
+; X86-NEXT:    pushl %edx
 ; X86-NEXT:    .cfi_adjust_cfa_offset 4
 ; X86-NEXT:    pushl %eax
 ; X86-NEXT:    .cfi_adjust_cfa_offset 4

diff --git a/llvm/test/CodeGen/X86/pr32284.ll b/llvm/test/CodeGen/X86/pr32284.ll
index 5d5a315ac74f8dca4de3619519c29ed94db16141..2ffb46209c344ee8f23d3b9d3ab385fa8a9dcbe4 100644 (file)
--- a/llvm/test/CodeGen/X86/pr32284.ll
+++ b/llvm/test/CodeGen/X86/pr32284.ll
@@ -268,9 +268,9 @@ define void @f1() {
 ; 686-NEXT:    sete %cl
 ; 686-NEXT:    xorl %edi, %edi
 ; 686-NEXT:    addl $7093, %edx # imm = 0x1BB5
-; 686-NEXT:    adcxl %edi, %esi
+; 686-NEXT:    adcxl %esi, %edi
 ; 686-NEXT:    cmpl %ecx, %edx
-; 686-NEXT:    sbbl $0, %esi
+; 686-NEXT:    sbbl $0, %edi
 ; 686-NEXT:    setl %cl
 ; 686-NEXT:    movzbl %cl, %ecx
 ; 686-NEXT:    movl %ecx, var_57