aarch64-option-extensions.def explicitly defines the semantics for an empty midr
field as being:
In that case this field
should contain a space (" ") separated list of the strings in 'Features'
that are required. Their order is not important. An empty string means
do not detect this feature during auto detection.
That is to say, an empty string means that we don't know the midr value for this
feature and so it just shouldn't be taken into account for native features
detection. However this meaning seems to have gotten lost at some point.
This results in e.g. -mcpu=native on a Neoverse N2 disabling features it does
have. Essentially we disabled any mandatory feature for which there is no midr
entry.
The rationale for having -mcpu=native being able to disable features at all, is
because the kernel is able to disable a mandatory feature for correctness
issues. Unfortunately we can't distinguish between "old kernel"
and "kernel disabled".
This patch adds a new field that indicates whether the midr field has any value
at all. If there's no value we skip the extension when determining the "off"
flags.
gcc/ChangeLog:
* common/config/aarch64/aarch64-common.cc
(struct aarch64_option_extension): Add native_detect and document struct
a bit more.
(all_extensions): Set new field native_detect.
* config/aarch64/aarch64.cc (struct aarch64_option_extension): Delete
unused struct.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/cpunative/info_19: New test.
* gcc.target/aarch64/cpunative/info_20: New test.
* gcc.target/aarch64/cpunative/info_21: New test.
* gcc.target/aarch64/cpunative/info_22: New test.
* gcc.target/aarch64/cpunative/native_cpu_19.c: New test.
* gcc.target/aarch64/cpunative/native_cpu_20.c: New test.
* gcc.target/aarch64/cpunative/native_cpu_21.c: New test.
* gcc.target/aarch64/cpunative/native_cpu_22.c: New test.
/* An ISA extension in the co-processor and main instruction set space. */
struct aarch64_option_extension
{
+ /* The extension name to pass on to the assembler. */
const char *name;
+ /* The smallest set of feature bits to toggle to enable this option. */
aarch64_feature_flags flag_canonical;
+ /* If this feature is turned on, these bits also need to be turned on. */
aarch64_feature_flags flags_on;
+ /* If this feature is turned off, these bits also need to be turned off. */
aarch64_feature_flags flags_off;
+ /* Indicates whether this feature is taken into account during native cpu
+ detection. */
+ bool native_detect_p;
};
/* ISA extensions in AArch64. */
static constexpr aarch64_option_extension all_extensions[] =
{
-#define AARCH64_OPT_EXTENSION(NAME, IDENT, C, D, E, F) \
+#define AARCH64_OPT_EXTENSION(NAME, IDENT, C, D, E, FEATURE_STRING) \
{NAME, AARCH64_FL_##IDENT, feature_deps::IDENT ().explicit_on, \
- feature_deps::get_flags_off (feature_deps::root_off_##IDENT)},
+ feature_deps::get_flags_off (feature_deps::root_off_##IDENT), \
+ FEATURE_STRING[0]},
#include "config/aarch64/aarch64-option-extensions.def"
- {NULL, 0, 0, 0}
+ {NULL, 0, 0, 0, false}
};
struct processor_name_to_arch
outstr += opt.name;
}
- /* Remove the features in current_flags & ~isa_flags. */
+ /* Remove the features in current_flags & ~isa_flags. If the feature does
+ not have an HWCAPs then it shouldn't be taken into account for feature
+ detection because one way or another we can't tell if it's available
+ or not. */
for (auto &opt : all_extensions)
- if (opt.flag_canonical & current_flags & ~isa_flags)
+ if (opt.native_detect_p
+ && (opt.flag_canonical & current_flags & ~isa_flags))
{
current_flags &= ~opt.flags_off;
outstr += "+no";
{ NULL, 0, 0, false, false, false, false, NULL, NULL }
};
-/* An ISA extension in the co-processor and main instruction set space. */
-struct aarch64_option_extension
-{
- const char *const name;
- const unsigned long flags_on;
- const unsigned long flags_off;
-};
-
typedef enum aarch64_cond_code
{
AARCH64_EQ = 0, AARCH64_NE, AARCH64_CS, AARCH64_CC, AARCH64_MI, AARCH64_PL,
--- /dev/null
+processor : 0
+BogoMIPS : 100.00
+Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 sve asimdfhm dit uscat ilrcpc flagm ssbs sb dcpodp sve2 sveaes svepmull svebitperm svesha3 svesm4 flagm2 frint svei8mm svebf16 i8mm bf16 dgh bti
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant : 0x0
+CPU part : 0xd49
+CPU revision : 2
+
--- /dev/null
+processor : 0
+BogoMIPS : 100.00
+Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 sve asimdfhm dit uscat ilrcpc flagm ssbs sb dcpodp sve2 sveaes svepmull svebitperm svesha3 svesm4 flagm2 frint svei8mm svebf16 i8mm bf16 dgh bti paca pacg
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant : 0x0
+CPU part : 0xd49
+CPU revision : 2
+
--- /dev/null
+processor : 0
+BogoMIPS : 100.00
+Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 sve asimdfhm dit uscat ilrcpc flagm ssbs sb dcpodp sve2 sveaes svepmull svebitperm svesha3 svesm4 flagm2 frint svei8mm svebf16 i8mm bf16 dgh bti
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant : 0x0
+CPU part : 0xd08
+CPU revision : 2
+
--- /dev/null
+processor : 0
+BogoMIPS : 100.00
+Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 sve asimdfhm dit uscat ilrcpc flagm ssbs sb dcpodp sve2 sveaes svepmull svebitperm svesha3 svesm4 flagm2 frint svei8mm svebf16 i8mm bf16 dgh bti paca pacg
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant : 0x0
+CPU part : 0xd08
+CPU revision : 2
+
--- /dev/null
+/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */
+/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_19" } */
+/* { dg-additional-options "-mcpu=native" } */
+
+int main()
+{
+ return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv9-a\+crc\+profile\+memtag\+sve2-sm4\+sve2-aes\+sve2-sha3\+sve2-bitperm\+i8mm\+bf16\+nopauth\n} } } */
+
+/* Test one that if the kernel doesn't report the availability of a mandatory
+ feature that it has turned it off for whatever reason. As such compilers
+ should follow along. */
--- /dev/null
+/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */
+/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_20" } */
+/* { dg-additional-options "-mcpu=native" } */
+
+int main()
+{
+ return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv9-a\+crc\+profile\+memtag\+sve2-sm4\+sve2-aes\+sve2-sha3\+sve2-bitperm\+i8mm\+bf16\n} } } */
+
+/* Check whether features that don't have a midr name during detection are
+ correctly ignored. These features shouldn't affect the native detection.
+ This particular test checks that predres is not turned off during
+ detection. */
--- /dev/null
+/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */
+/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_21" } */
+/* { dg-additional-options "-mcpu=native" } */
+
+int main()
+{
+ return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8-a\+crc\+lse\+rcpc\+rdma\+dotprod\+fp16fml\+sb\+ssbs\+sve2-sm4\+sve2-aes\+sve2-sha3\+sve2-bitperm\+i8mm\+bf16\+flagm\n} } } */
+
+/* Check that an Armv8-A core doesn't fall apart on extensions without midr
+ values. */
--- /dev/null
+/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */
+/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_22" } */
+/* { dg-additional-options "-mcpu=native" } */
+
+int main()
+{
+ return 0;
+}
+
+/* { dg-final { scan-assembler {\.arch armv8-a\+crc\+lse\+rcpc\+rdma\+dotprod\+fp16fml\+sb\+ssbs\+sve2-sm4\+sve2-aes\+sve2-sha3\+sve2-bitperm\+i8mm\+bf16\+flagm\+pauth\n} } } */
+
+/* Check that an Armv8-A core doesn't fall apart on extensions without midr
+ values and that it enables optional features. */
projects / platform / upstream / gcc.git / commitdiff