net: phylink: add phylink_set_10g_modes() helper
authorRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
Mon, 4 Oct 2021 11:03:28 +0000 (12:03 +0100)
committerDavid S. Miller <davem@davemloft.net>
Mon, 4 Oct 2021 12:50:05 +0000 (13:50 +0100)
Add a helper for setting 10Gigabit modes, so we have one central
place that sets all appropriate 10G modes for a driver.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/phy/phylink.c
include/linux/phylink.h

index 5a58c77..b32774f 100644 (file)
@@ -132,6 +132,17 @@ void phylink_set_port_modes(unsigned long *mask)
 }
 EXPORT_SYMBOL_GPL(phylink_set_port_modes);
 
+void phylink_set_10g_modes(unsigned long *mask)
+{
+       phylink_set(mask, 10000baseT_Full);
+       phylink_set(mask, 10000baseCR_Full);
+       phylink_set(mask, 10000baseSR_Full);
+       phylink_set(mask, 10000baseLR_Full);
+       phylink_set(mask, 10000baseLRM_Full);
+       phylink_set(mask, 10000baseER_Full);
+}
+EXPORT_SYMBOL_GPL(phylink_set_10g_modes);
+
 static int phylink_is_empty_linkmode(const unsigned long *linkmode)
 {
        __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp) = { 0, };
index 2372911..f7b5ed0 100644 (file)
@@ -484,6 +484,7 @@ int phylink_speed_up(struct phylink *pl);
 #define phylink_test(bm, mode) __phylink_do_bit(test_bit, bm, mode)
 
 void phylink_set_port_modes(unsigned long *bits);
+void phylink_set_10g_modes(unsigned long *mask);
 void phylink_helper_basex_speed(struct phylink_link_state *state);
 
 void phylink_mii_c22_pcs_get_state(struct mdio_device *pcs,