cxl/region: fix x9 interleave typo

[ Upstream commit c7ad3dc3649730af483ee1e78be5d0362da25bfe ]

CXL supports x3, x6 and x12 - not x9.

Fixes: 80d10a6cee050 ("cxl/region: Add interleave geometry attributes")
Signed-off-by: Jim Harris <jim.harris@samsung.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Link: https://lore.kernel.org/r/169904271254.204936.8580772404462743630.stgit@ubuntu
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
index e7206367ec6698e837d72ff82e6f77b609d371cf..472bd510b5e27cc3341f55e6fbe495dbc68a717a 100644 (file)
--- a/drivers/cxl/core/region.c
+++ b/drivers/cxl/core/region.c
@@ -397,7 +397,7 @@ static ssize_t interleave_ways_store(struct device *dev,
                return rc;
 
        /*
-        * Even for x3, x9, and x12 interleaves the region interleave must be a
+        * Even for x3, x6, and x12 interleaves the region interleave must be a
         * power of 2 multiple of the host bridge interleave.
         */
        if (!is_power_of_2(val / cxld->interleave_ways) ||