mxc: Fix SDHC multi-instance clock
authorBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Mon, 1 Oct 2012 08:36:25 +0000 (08:36 +0000)
committerStefano Babic <sbabic@denx.de>
Tue, 16 Oct 2012 10:35:10 +0000 (12:35 +0200)
On mxc, each SDHC instance has a dedicated clock, so gd->sdhc_clk is not
suitable for the multi-instance use case (initialization made directly with
fsl_esdhc_initialize()).

This patch fixes this issue by adding a configuration field for the SDHC input
clock frequency.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Eric Bénard <eric@eukrea.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Jason Liu <r64343@freescale.com>
Cc: Matt Sealey <matt@genesi-usa.com>
Cc: Andy Fleming <afleming@gmail.com>
15 files changed:
board/esg/ima3-mx53/ima3-mx53.c
board/freescale/mx35pdk/mx35pdk.c
board/freescale/mx51evk/mx51evk.c
board/freescale/mx53ard/mx53ard.c
board/freescale/mx53evk/mx53evk.c
board/freescale/mx53loco/mx53loco.c
board/freescale/mx53smd/mx53smd.c
board/freescale/mx6qarm2/mx6qarm2.c
board/freescale/mx6qsabreauto/mx6qsabreauto.c
board/freescale/mx6qsabrelite/mx6qsabrelite.c
board/freescale/mx6qsabresd/mx6qsabresd.c
board/genesi/mx51_efikamx/efikamx.c
board/ttcontrol/vision2/vision2.c
drivers/mmc/fsl_esdhc.c
include/fsl_esdhc.h

index e947330..41d6bb6 100644 (file)
@@ -217,6 +217,7 @@ int board_mmc_init(bd_t *bis)
                PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
                PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 
+       esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
        return fsl_esdhc_initialize(bis, &esdhc_cfg);
 }
 #endif
index 7cb6b30..a12531f 100644 (file)
@@ -27,6 +27,7 @@
 #include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/mx35_pins.h>
 #include <asm/arch/iomux.h>
 #include <i2c.h>
@@ -292,6 +293,7 @@ int board_mmc_init(bd_t *bis)
        mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC);
        mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC);
 
+       esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
        return fsl_esdhc_initialize(bis, &esdhc_cfg);
 }
 
index a94701c..3412952 100644 (file)
@@ -29,6 +29,7 @@
 #include <asm/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <i2c.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
@@ -358,6 +359,9 @@ int board_mmc_init(bd_t *bis)
        u32 index;
        s32 status = 0;
 
+       esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+       esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
        for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
                        index++) {
                switch (index) {
index 08c7795..2fc8570 100644 (file)
@@ -26,6 +26,7 @@
 #include <asm/arch/mx5x_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>
 #include <asm/errno.h>
 #include <netdev.h>
@@ -106,6 +107,9 @@ int board_mmc_init(bd_t *bis)
        u32 index;
        s32 status = 0;
 
+       esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+       esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
        for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
                switch (index) {
                case 0:
index b11a94c..bb4621d 100644 (file)
@@ -26,6 +26,7 @@
 #include <asm/arch/mx5x_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>
 #include <asm/errno.h>
 #include <asm/imx-common/boot_mode.h>
@@ -232,6 +233,9 @@ int board_mmc_init(bd_t *bis)
        u32 index;
        s32 status = 0;
 
+       esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+       esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
        for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
                switch (index) {
                case 0:
index 6543209..20569a5 100644 (file)
@@ -192,6 +192,9 @@ int board_mmc_init(bd_t *bis)
        u32 index;
        s32 status = 0;
 
+       esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+       esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
        for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
                switch (index) {
                case 0:
index 7f35ddd..761f727 100644 (file)
@@ -26,6 +26,7 @@
 #include <asm/arch/mx5x_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>
 #include <asm/errno.h>
 #include <netdev.h>
@@ -144,6 +145,8 @@ int board_mmc_init(bd_t *bis)
        u32 index;
        s32 status = 0;
 
+       esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
        for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
                switch (index) {
                case 0:
index d43b327..dad4b95 100644 (file)
@@ -24,6 +24,7 @@
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/mx6x_pins.h>
+#include <asm/arch/clock.h>
 #include <asm/errno.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
@@ -139,6 +140,9 @@ int board_mmc_init(bd_t *bis)
        s32 status = 0;
        u32 index = 0;
 
+       usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+       usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
        for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
                switch (index) {
                case 0:
index fcd83dc..17ff8ff 100644 (file)
@@ -114,6 +114,7 @@ int board_mmc_init(bd_t *bis)
 {
        imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 
+       usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
        return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 }
 #endif
index 4b4e89b..3af8437 100644 (file)
@@ -264,6 +264,9 @@ int board_mmc_init(bd_t *bis)
        s32 status = 0;
        u32 index = 0;
 
+       usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+       usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
        for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
               switch (index) {
               case 0:
index 03a6857..e02daa4 100644 (file)
@@ -120,6 +120,7 @@ int board_mmc_init(bd_t *bis)
 {
        imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 
+       usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
        return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 }
 #endif
index cfd2e93..e334c01 100644 (file)
@@ -29,6 +29,7 @@
 #include <asm/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <i2c.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
@@ -349,6 +350,9 @@ int board_mmc_init(bd_t *bis)
                gpio_direction_input(EFIKASB_SDHC1_CD);
        }
 
+       esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+       esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
        ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 
        if (machine_is_efikasb()) {
index f28eab0..ba3307b 100644 (file)
@@ -28,6 +28,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/mx5x_pins.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>
 #include <asm/gpio.h>
 #include <asm/arch/sys_proto.h>
@@ -590,6 +591,7 @@ int board_mmc_init(bd_t *bis)
        mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
                PAD_CTL_HYS_ENABLE);
 
+       esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
        return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 }
 #endif
index 3f8d30d..aa6a9f1 100644 (file)
@@ -410,12 +410,12 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
        return 0;
 }
 
-void set_sysctl(struct mmc *mmc, uint clock)
+static void set_sysctl(struct mmc *mmc, uint clock)
 {
-       int sdhc_clk = gd->sdhc_clk;
        int div, pre_div;
        struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
        volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+       int sdhc_clk = cfg->sdhc_clk;
        uint clk;
 
        if (clock < mmc->f_min)
@@ -598,6 +598,7 @@ int fsl_esdhc_mmc_init(bd_t *bis)
        cfg = malloc(sizeof(struct fsl_esdhc_cfg));
        memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
        cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
+       cfg->sdhc_clk = gd->sdhc_clk;
        return fsl_esdhc_initialize(bis, cfg);
 }
 
index 4e321e7..47d2fe4 100644 (file)
 
 struct fsl_esdhc_cfg {
        u32     esdhc_base;
+       u32     sdhc_clk;
 };
 
 /* Select the correct accessors depending on endianess */