}}
sp = cast(void*)®s[0];
}
+ else version (AArch64)
+ {
+ // Callee-save registers, x19-x28 according to AAPCS64, section
+ // 5.1.1. Include x29 fp because it optionally can be a callee
+ // saved reg
+ size_t[11] regs = void;
+ // store the registers in pairs
+ asm pure nothrow @nogc
+ {
+ "stp x19, x20, %0" : "=m" (regs[ 0]), "=m" (regs[1]);
+ "stp x21, x22, %0" : "=m" (regs[ 2]), "=m" (regs[3]);
+ "stp x23, x24, %0" : "=m" (regs[ 4]), "=m" (regs[5]);
+ "stp x25, x26, %0" : "=m" (regs[ 6]), "=m" (regs[7]);
+ "stp x27, x28, %0" : "=m" (regs[ 8]), "=m" (regs[9]);
+ "str x29, %0" : "=m" (regs[10]);
+ "mov %0, sp" : "=r" (sp);
+ }
+ }
+ else version (ARM)
+ {
+ // Callee-save registers, according to AAPCS, section 5.1.1.
+ // arm and thumb2 instructions
+ size_t[8] regs = void;
+ asm pure nothrow @nogc
+ {
+ "stm %0, {r4-r11}" : : "r" (regs.ptr) : "memory";
+ "mov %0, sp" : "=r" (sp);
+ }
+ }
else
{
__builtin_unwind_init();