mt76_wr(dev, MT_TMAC_TRCR1, val);
val = MT_AGG_ACR_PKT_TIME_EN | MT_AGG_ACR_NO_BA_AR_RULE |
- FIELD_PREP(MT_AGG_ACR_CFEND_RATE, 0x49) | /* 24M */
- FIELD_PREP(MT_AGG_ACR_BAR_RATE, 0x4b); /* 6M */
+ FIELD_PREP(MT_AGG_ACR_CFEND_RATE, MT7615_CFEND_RATE_DEFAULT) |
+ FIELD_PREP(MT_AGG_ACR_BAR_RATE, MT7615_BAR_RATE_DEFAULT);
mt76_wr(dev, MT_AGG_ACR0, val);
mt76_wr(dev, MT_AGG_ACR1, val);
#define MT_CHFREQ_DBDC_IDX BIT(6)
#define MT_CHFREQ_SEQ GENMASK(5, 0)
-#define MT7615_CFEND_RATE_DEFAULT 0x69 /* chip default (24M) */
+#define MT7615_BAR_RATE_DEFAULT 0x4b /* OFDM 6M */
+#define MT7615_CFEND_RATE_DEFAULT 0x49 /* OFDM 24M */
#define MT7615_CFEND_RATE_11B 0x03 /* 11B LP, 11M */
struct mt7615_vif;