for (i = 3, j = 30; i <= last_parm_reg; i++, j--)
fprintf (file, "\tai %d,%d,0\n", i, j);
}
+
+/* Adjust the cost of a scheduling dependency. Return the new cost of
+ a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
+
+int
+ppc_adjust_cost (insn, link, dep_insn, cost)
+ rtx insn;
+ rtx link;
+ rtx dep_insn;
+ int cost;
+{
+ if (! recog_memoized (insn))
+ return 0;
+
+ if (REG_NOTE_KIND (link) != 0)
+ return 0;
+
+ if (REG_NOTE_KIND (link) == 0)
+ {
+ /* Data dependency; DEP_INSN writes a register that INSN reads some
+ cycles later. */
+
+ /* Tell the first scheduling pass about the latency between a mtctr
+ and bctr (and mtlr and br/blr). The first scheduling pass will not
+ know about this latency since the mtctr instruction, which has the
+ latency associated to it, will be generated by reload. */
+ if (get_attr_type (insn) == TYPE_JMPREG)
+ return TARGET_POWER ? 5 : 4;
+
+ /* Fall out to return default cost. */
+ }
+
+ return cost;
+}