ac/gpu_info: add radeon_info::num_tcc_blocks

The values for the radeon winsys were copied from the kernel driver.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index e885c05..40441ec 100644 (file)
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -96,6 +96,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
                       struct radeon_info *info,
                       struct amdgpu_gpu_info *amdinfo)
 {
+       struct drm_amdgpu_info_device device_info = {};
        struct amdgpu_buffer_size_alignments alignment_info = {};
        struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
        struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {};
@@ -124,6 +125,13 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
                return false;
        }
 
+       r = amdgpu_query_info(dev, AMDGPU_INFO_DEV_INFO, sizeof(device_info),
+                             &device_info);
+       if (r) {
+               fprintf(stderr, "amdgpu: amdgpu_query_info(dev_info) failed.\n");
+               return false;
+       }
+
        r = amdgpu_query_buffer_size_alignment(dev, &alignment_info);
        if (r) {
                fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
@@ -324,6 +332,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
        info->gds_gfx_partition_size = gds.gds_gfx_partition_size;
        /* convert the shader clock from KHz to MHz */
        info->max_shader_clock = amdinfo->max_engine_clk / 1000;
+       info->num_tcc_blocks = device_info.num_tcc_blocks;
        info->max_se = amdinfo->num_shader_engines;
        info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
        info->has_hw_decode =
@@ -530,6 +539,7 @@ void ac_print_gpu_info(struct radeon_info *info)
        printf("Shader core info:\n");
        printf("    max_shader_clock = %i\n", info->max_shader_clock);
        printf("    num_good_compute_units = %i\n", info->num_good_compute_units);
+       printf("    num_tcc_blocks = %i\n", info->num_tcc_blocks);
        printf("    max_se = %i\n", info->max_se);
        printf("    max_sh_per_se = %i\n", info->max_sh_per_se);
 

diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 1201d81..f6e09d2 100644 (file)
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -115,6 +115,7 @@ struct radeon_info {
        uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
        uint32_t                    max_shader_clock;
        uint32_t                    num_good_compute_units;
+       uint32_t                    num_tcc_blocks;
        uint32_t                    max_se; /* shader engines */
        uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 76eea67..86df2ac 100644 (file)
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -471,6 +471,32 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SE, NULL,
                          &ws->info.max_se);
 
+    switch (ws->info.family) {
+    case CHIP_HAINAN:
+    case CHIP_KABINI:
+    case CHIP_MULLINS:
+        ws->info.num_tcc_blocks = 2;
+        break;
+    case CHIP_VERDE:
+    case CHIP_OLAND:
+    case CHIP_BONAIRE:
+    case CHIP_KAVERI:
+        ws->info.num_tcc_blocks = 4;
+        break;
+    case CHIP_PITCAIRN:
+        ws->info.num_tcc_blocks = 8;
+        break;
+    case CHIP_TAHITI:
+        ws->info.num_tcc_blocks = 12;
+        break;
+    case CHIP_HAWAII:
+        ws->info.num_tcc_blocks = 16;
+        break;
+    default:
+        ws->info.num_tcc_blocks = 0;
+        break;
+    }
+
     if (!ws->info.max_se) {
         switch (ws->info.family) {
         default: